Open-Source Phased Array Radar

# Engineering Documentation Site

This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.

View Change Timeline Open Readiness Package

## Tracked Timing Baseline

WNS +0.058 ns

WHS +0.068, WPWS +0.684 after validated Build 16 XDC port

## Regression Status

MCU 15 / 15, FPGA 18 / 18

Host firmware regression plus FPGA unit and integration suites passing

## Methodology State

XDCB-5 = 0

Single documented TIMING-18 residue on `ft601_txe` async observation

## Current Phase

Pre-Hardware Readiness

Board-arrival smoke test, artifact inventory, and open-risk tracking prepared

## What changed recently

- Ported the validated Build 16 production-target XDC cleanup into the tracked repository.
- Preserved positive post-route timing while clearing XDCB-5 and reducing methodology residue to a single documented item.
- Validated the tracked branch with MCU host regression and FPGA regression/integration suites.
- Refreshed the bring-up documentation into a pre-arrival readiness package for the FPGA module and carrier board.
- Kept upstream ADAR1000 bulk imports out of the baseline pending selective, justified reuse only.

## Documentation Map

- System and FPGA Architecture
- Detailed Engineering Change Log
- Pre-Arrival Bring-Up Plan, Artifact Checklist, and Open Risks
- Published reports, simulations, and artifact context
- Release Notes by Key Commit