From 166464e8774462aedeb4e0ac20d3928267e64bc6 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Sat, 2 May 2026 10:20:10 +0545 Subject: [PATCH] =?UTF-8?q?fix(fpga):=20PR-O.8.1=20=E2=80=94=20drop=20stal?= =?UTF-8?q?e=20BFP-era=20ports,=20fix=20xsim=20include=20path?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrapper xfft_2048.v had m_axis_data_tuser and m_axis_status_{tdata,tvalid, tready} hooked up to the IP, but the regenerated xfft_2048_ip in scaled mode + Pipelined Streaming + 1 channel + no XK_INDEX/OVFLO doesn't expose those ports. xelab errored "cannot find port" on all four. Removed. run_xfft_xsim.sh missed -i "$PROJ_ROOT" so xvlog couldn't resolve `include "radar_params.vh"` from inside tb/. Fixed. gen_xfft_2048_ip.tcl header comment described the old Burst I/O 11-stage schedule; updated to PG109 Pipelined Streaming pair-grouped layout that matches the actual SCALE_SCH = 12'hAA9 we now drive. Verified: tb_xfft_2048_xsim 5/5 PASS on real LogiCORE FFT v9.1 IP under Vivado 2025.2 xsim — DC peak at bin 0, impulse flat spectrum, tone at bin 128. Closes T-10 (FFT-block synth-mode validation). --- .../9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl | 4 +++- .../9_2_FPGA/scripts/50t/run_xfft_xsim.sh | 5 +++-- 9_Firmware/9_2_FPGA/xfft_2048.v | 22 ++++++------------- 3 files changed, 13 insertions(+), 18 deletions(-) diff --git a/9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl b/9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl index f09d90f..0e68efc 100644 --- a/9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl +++ b/9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl @@ -6,7 +6,9 @@ # - Architecture: Pipelined Streaming I/O (Radix-2, 11 stages) # - Data Format: Fixed Point # - Scaling: Scaled (fixed schedule via cfg_tdata SCALE_SCH bits) -# Schedule [1,1,1,1,1,1,1,1,1,1,1] = /N (unitary FFT). +# Schedule = 12'hAA9 (PG109 Pipelined Streaming layout): +# stage 1 alone >>1, stages 2-3, 4-5, 6-7, 8-9, 10-11 +# grouped each >>2 (per pair). Total = /N = unitary FFT. # AUDIT-C10/C-8 resolution: BFP previously hid a per-frame # block exponent the bridge dropped, making sim/silicon # absolute magnitudes incomparable. Scaled mode locks a diff --git a/9_Firmware/9_2_FPGA/scripts/50t/run_xfft_xsim.sh b/9_Firmware/9_2_FPGA/scripts/50t/run_xfft_xsim.sh index b943c86..2467960 100644 --- a/9_Firmware/9_2_FPGA/scripts/50t/run_xfft_xsim.sh +++ b/9_Firmware/9_2_FPGA/scripts/50t/run_xfft_xsim.sh @@ -23,8 +23,9 @@ mkdir -p "$WORK_DIR" cd "$WORK_DIR" echo "===== Compiling Verilog sources =====" -# Wrapper + testbench with the IP-on define -xvlog -d FFT_USE_XILINX_IP "$WRAPPER" "$TB" +# Wrapper + testbench with the IP-on define. -i adds the FPGA root so +# `include "radar_params.vh"` resolves from inside tb/. +xvlog -d FFT_USE_XILINX_IP -i "$PROJ_ROOT" "$WRAPPER" "$TB" # IP simulation netlist — references unisim primitives xvlog "$IP_NETLIST" # fft_engine etc. NOT needed because FFT_USE_XILINX_IP routes around it, diff --git a/9_Firmware/9_2_FPGA/xfft_2048.v b/9_Firmware/9_2_FPGA/xfft_2048.v index 65c9e37..e1ddcee 100644 --- a/9_Firmware/9_2_FPGA/xfft_2048.v +++ b/9_Firmware/9_2_FPGA/xfft_2048.v @@ -56,8 +56,8 @@ module xfft_2048 ( output wire s_axis_data_tready, // Data output channel (AXI-Stream master). 64-bit packed {Q[31:0], I[31:0]}. - // No tuser — scaled mode does not emit BLK_EXP, and the design has no - // XK_INDEX / OVFLO consumers. + // No tuser — scaled mode does not emit BLK_EXP, and the IP is configured + // with no XK_INDEX / OVFLO outputs (see gen_xfft_2048_ip.tcl). output wire [63:0] m_axis_data_tdata, output wire m_axis_data_tvalid, output wire m_axis_data_tlast, @@ -68,15 +68,11 @@ module xfft_2048 ( // ============================================================================ // XILINX LOGICORE FFT v9.1 — production / XSim path // ============================================================================ -// Side-channels (status/event) are tied off here; if downstream needs them -// (e.g. for pipeline-stall debug), surface them through this wrapper. - -wire [7:0] xfft_status_tdata; -wire xfft_status_tvalid; -// tuser still exists on the IP port surface (Vivado emits a 1-bit dummy in -// scaled mode with no XK_INDEX/OVFLO). Wired to a local sink so the placer -// elides it. -wire [7:0] xfft_dout_tuser_unused; +// Per the regenerated IP (Pipelined Streaming + scaled + 1 channel + no CP + +// no XK_INDEX / no OVFLO), the IP exposes only the AXI-Stream config / data +// channels and six event signals. There is no m_axis_data_tuser and no +// m_axis_status_* channel in this configuration. Event signals are left +// unconnected — none are consumed downstream. xfft_2048_ip u_xfft ( .aclk (aclk), @@ -88,13 +84,9 @@ xfft_2048_ip u_xfft ( .s_axis_data_tready (s_axis_data_tready), .s_axis_data_tlast (s_axis_data_tlast), .m_axis_data_tdata (m_axis_data_tdata), - .m_axis_data_tuser (xfft_dout_tuser_unused), .m_axis_data_tvalid (m_axis_data_tvalid), .m_axis_data_tready (m_axis_data_tready), .m_axis_data_tlast (m_axis_data_tlast), - .m_axis_status_tdata (xfft_status_tdata), - .m_axis_status_tvalid (xfft_status_tvalid), - .m_axis_status_tready (1'b1), .event_frame_started (), .event_tlast_unexpected (), .event_tlast_missing (),