From 3d0ee509995cb71045aa34fc65c55f9cf5c6d0f5 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Wed, 22 Apr 2026 19:34:09 +0545
Subject: [PATCH] fix(fpga): reset chirp_counter at DONE; source CHIRP_MAX from
 radar_params

C-3: plfm_chirp_controller_enhanced never reset chirp_counter when the
frame completed. Counter sat at CHIRP_MAX after frame 1, so the
LONG_LISTEN -> GUARD transition guard (== CHIRP_MAX/2-1) never matched
correctly on subsequent frames and frame 2+ ran extra chirps until the
6-bit counter wrapped. Reset chirp_counter in the DONE state.

S-2: Replace hardcoded CHIRP_MAX = 32 with RP_CHIRPS_PER_FRAME from
radar_params.vh so the TX FSM tracks the single source of truth.

S-1: Correct misleading labels in tb_system_e2e G14.1-G14.3. Per
radar_params.vh the range_mode encoding is 2'b00 = 3 km, 2'b01 =
long-range, 2'b10/2'b11 = reserved. The TB strings previously called
2'b01 "short" and 2'b10 "long", which is inverted and inconsistent
with the RTL comments in radar_mode_controller.v.

Regression: 32/32 PASS.
---
 9_Firmware/9_2_FPGA/plfm_chirp_controller.v |  9 ++++++++-
 9_Firmware/9_2_FPGA/tb/tb_system_e2e.v      | 12 ++++++------
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/9_Firmware/9_2_FPGA/plfm_chirp_controller.v b/9_Firmware/9_2_FPGA/plfm_chirp_controller.v
index 884a0f4..4b70ebb 100644
--- a/9_Firmware/9_2_FPGA/plfm_chirp_controller.v
+++ b/9_Firmware/9_2_FPGA/plfm_chirp_controller.v
@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 module plfm_chirp_controller_enhanced (
     input wire clk_120m,
     input wire clk_100m,
@@ -45,7 +47,7 @@ parameter T2_RADAR_LISTENING = 20940; //174.5us at 120MHz
 parameter GUARD_SAMPLES = 21048;    // 175.4us at 120MHz
 
 // Chirp and beam parameters
-parameter CHIRP_MAX = 32;
+parameter CHIRP_MAX = `RP_CHIRPS_PER_FRAME;
 parameter ELEVATION_MAX = 31;
 parameter AZIMUTH_MAX = 50;
 
@@ -320,6 +322,11 @@ always @(posedge clk_120m or negedge reset_n) begin
             end
             
             DONE: begin
+                // Reset chirp_counter so the next frame restarts at chirp 0.
+                // Without this, frame 2+ starts at chirp_counter == CHIRP_MAX
+                // and the LONG_LISTEN transition guard (== CHIRP_MAX/2-1)
+                // never matches on the correct chirp.
+                chirp_counter <= 0;
                 chirp_done <= 1'b1;
                 chirp_data <= 8'd128;
             end
diff --git a/9_Firmware/9_2_FPGA/tb/tb_system_e2e.v b/9_Firmware/9_2_FPGA/tb/tb_system_e2e.v
index 51b35f0..87de989 100644
--- a/9_Firmware/9_2_FPGA/tb/tb_system_e2e.v
+++ b/9_Firmware/9_2_FPGA/tb/tb_system_e2e.v
@@ -1161,20 +1161,20 @@ initial begin
     // The registers were re-loaded in G9. Send fresh values to verify write path.
 
     // --- Range Mode Register (0x20, Fix 7) ---
-    // G14.1: Set range_mode to short-range (0x01)
+    // G14.1: Set range_mode to long-range (0x01)
     bfm_send_cmd(8'h20, 8'h00, 16'h0001);
     check(dut.host_range_mode == 2'b01,
-          "G14.1: Opcode 0x20 -> host_range_mode = 2'b01 (short)");
+          "G14.1: Opcode 0x20 -> host_range_mode = 2'b01 (long-range)");
 
-    // G14.2: Set range_mode to long-range (0x02)
+    // G14.2: Set range_mode to reserved value 0x02 (permissive: stored as-is)
     bfm_send_cmd(8'h20, 8'h00, 16'h0002);
     check(dut.host_range_mode == 2'b10,
-          "G14.2: Opcode 0x20 -> host_range_mode = 2'b10 (long)");
+          "G14.2: Opcode 0x20 -> host_range_mode = 2'b10 (reserved)");
 
-    // G14.3: Restore range_mode to auto (0x00)
+    // G14.3: Restore range_mode to 3 km (0x00)
     bfm_send_cmd(8'h20, 8'h00, 16'h0000);
     check(dut.host_range_mode == 2'b00,
-          "G14.3: Opcode 0x20 -> host_range_mode = 2'b00 (auto)");
+          "G14.3: Opcode 0x20 -> host_range_mode = 2'b00 (3 km)");
 
     // --- CFAR Guard Cells (0x21) ---
     // G14.4: Set guard cells to 4