feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

File-scoped cherry-pick from feat/fft-2048-upgrade (e9705e4) for modules
that only the fft branch modified:

  RTL:
    cfar_ca.v                        512-row CFAR
    chirp_memory_loader_param.v      2-segment × 2048-sample loader
    doppler_processor.v              16384-deep doppler memory
    fft_engine.v                     2048-pt FFT
    matched_filter_multi_segment.v   2-seg overlap-save, BRAM overlap_cache
    matched_filter_processing_chain.v
    radar_mode_controller.v          XOR edge detector
    radar_params.vh                  (new) single source of truth
    range_bin_decimator.v            2048 -> 512 output bins
    rx_gain_control.v

  Memory:
    fft_twiddle_2048.mem             (new) 2048-pt FFT twiddles
    long_chirp_seg0_{i,q}.mem        2048-sample seg 0 (was 1024)
    long_chirp_seg1_{i,q}.mem        2048-sample seg 1 (was 1024)
    long_chirp_seg{2,3}_{i,q}.mem    deleted (4-seg -> 2-seg collapse)

  Gen:
    tb/cosim/gen_chirp_mem.py        regen script for mem files above

Waves 2 and 3 follow: manual merge for dual-modified files
(radar_system_top, usb_data_interface_ft2232h, mti_canceller,
radar_receiver_final), and CFAR pipeline from 2401f5f keeping p0's
CIC/DDC reset strategy.

9_Firmware/9_2_FPGA/cfar_ca.v

@@ -16,9 +16,9 @@
  *
  *   Phase 2 (CFAR): After frame_complete pulse from Doppler processor,
  *     process each Doppler column independently:
- *     a) Read 64 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
+ *     a) Read 512 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
  *     b) Compute initial sliding window sums (ST_CFAR_INIT)
- *     c) Slide CUT through all 64 range bins:
+ *     c) Slide CUT through all 512 range bins:
  *        - 3 sub-cycles per CUT:
  *          ST_CFAR_THR: register noise_sum (mode select + cross-multiply)
  *          ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
@@ -47,21 +47,23 @@
  *   typically clutter).
  *
  * Timing:
- *   Phase 2 takes ~(66 + T + 3*64) * 32 ≈ 8500 cycles per frame @ 100 MHz
- *   = 85 µs. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
+ *   Phase 2 takes ~(514 + T + 3*512) * 32 ≈ 55000 cycles per frame @ 100 MHz
+ *   = 0.55 ms. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
  *   (3 cycles per CUT due to pipeline: THR → MUL → CMP)
  *
  * Resources:
- *   - 1 BRAM18K for magnitude buffer (2048 x 17 bits)
+ *   - 1 BRAM36K for magnitude buffer (16384 x 17 bits)
  *   - 1 DSP48 for alpha multiply
  *   - ~300 LUTs for FSM + sliding window + comparators
  *
  * Clock domain: clk (100 MHz, same as Doppler processor)
  */
 
+`include "radar_params.vh"
+
 module cfar_ca #(
-    parameter NUM_RANGE_BINS   = 64,
-    parameter NUM_DOPPLER_BINS = 32,
+    parameter NUM_RANGE_BINS   = `RP_NUM_RANGE_BINS,    // 512
+    parameter NUM_DOPPLER_BINS = `RP_NUM_DOPPLER_BINS,  // 32
     parameter MAG_WIDTH        = 17,
     parameter ALPHA_WIDTH      = 8,
     parameter MAX_GUARD        = 8,
@@ -74,7 +76,7 @@ module cfar_ca #(
     input wire [31:0] doppler_data,
     input wire        doppler_valid,
     input wire [4:0]  doppler_bin_in,
-    input wire [5:0]  range_bin_in,
+    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,  // 9-bit
     input wire        frame_complete,
 
     // ========== CONFIGURATION ==========
@@ -88,7 +90,7 @@ module cfar_ca #(
     // ========== DETECTION OUTPUTS ==========
     output reg        detect_flag,
     output reg        detect_valid,
-    output reg [5:0]  detect_range,
+    output reg [`RP_RANGE_BIN_BITS-1:0] detect_range,  // 9-bit
     output reg [4:0]  detect_doppler,
     output reg [MAG_WIDTH-1:0] detect_magnitude,
     output reg [MAG_WIDTH-1:0] detect_threshold,
@@ -103,11 +105,11 @@ module cfar_ca #(
 // INTERNAL PARAMETERS
 // ============================================================================
 localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
-localparam ADDR_WIDTH  = 11;
+localparam ADDR_WIDTH  = `RP_CFAR_MAG_ADDR_W;  // 14
 localparam COL_BITS    = 5;
-localparam ROW_BITS    = 6;
-localparam SUM_WIDTH   = MAG_WIDTH + 6;  // 23 bits: sum of up to 64 magnitudes
-localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 31 bits
+localparam ROW_BITS    = `RP_RANGE_BIN_BITS;    // 9
+localparam SUM_WIDTH   = MAG_WIDTH + ROW_BITS;  // 26 bits: sum of up to 512 magnitudes
+localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 34 bits
 localparam ALPHA_FRAC_BITS = 4;  // Q4.4
 
 // ============================================================================
@@ -136,7 +138,7 @@ wire [15:0] abs_q = dop_q[15] ? (~dop_q + 16'd1) : dop_q;
 wire [MAG_WIDTH-1:0] cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 
 // ============================================================================
-// MAGNITUDE BRAM (2048 x 17 bits)
+// MAGNITUDE BRAM (16384 x 17 bits)
 // ============================================================================
 reg                    mag_we;
 reg [ADDR_WIDTH-1:0]   mag_waddr;
@@ -153,7 +155,7 @@ always @(posedge clk) begin
 end
 
 // ============================================================================
-// COLUMN LINE BUFFER (64 x 17 bits — distributed RAM)
+// COLUMN LINE BUFFER (512 x 17 bits — BRAM)
 // ============================================================================
 reg [MAG_WIDTH-1:0] col_buf [0:NUM_RANGE_BINS-1];
 reg [ROW_BITS:0] col_load_idx;
@@ -206,20 +208,31 @@ wire lead_rem_valid = (lead_rem_idx >= 0) && (lead_rem_idx < NUM_RANGE_BINS);
 wire lag_rem_valid  = (lag_rem_idx  >= 0) && (lag_rem_idx  < NUM_RANGE_BINS);
 wire lag_add_valid  = (lag_add_idx  >= 0) && (lag_add_idx  < NUM_RANGE_BINS);
 
-// Safe col_buf read with bounds checking (combinational)
+// Safe col_buf read with bounds checking (combinational — feeds pipeline regs)
 wire [MAG_WIDTH-1:0] lead_add_val = lead_add_valid ? col_buf[lead_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lead_rem_val = lead_rem_valid ? col_buf[lead_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_rem_val  = lag_rem_valid  ? col_buf[lag_rem_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_add_val  = lag_add_valid  ? col_buf[lag_add_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 
-// Net deltas
-wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid ? $signed({1'b0, lead_add_val}) : 0)
-                                      - (lead_rem_valid ? $signed({1'b0, lead_rem_val}) : 0);
-wire signed [1:0] lead_cnt_delta = (lead_add_valid ? 1 : 0) - (lead_rem_valid ? 1 : 0);
+// ============================================================================
+// PIPELINE REGISTERS: Break col_buf mux tree out of ST_CFAR_CMP critical path
+// ============================================================================
+// Captured in ST_CFAR_THR (col_buf indices depend only on cut_idx/r_guard/r_train,
+// all stable during THR). Used in ST_CFAR_CMP for delta/sum computation.
+// This removes ~6-8 logic levels (9-level mux tree) from the CMP critical path.
+reg [MAG_WIDTH-1:0] lead_add_val_r, lead_rem_val_r;
+reg [MAG_WIDTH-1:0] lag_rem_val_r,  lag_add_val_r;
+reg                 lead_add_valid_r, lead_rem_valid_r;
+reg                 lag_rem_valid_r,  lag_add_valid_r;
 
-wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid ? $signed({1'b0, lag_add_val}) : 0)
-                                     - (lag_rem_valid ? $signed({1'b0, lag_rem_val}) : 0);
-wire signed [1:0] lag_cnt_delta = (lag_add_valid ? 1 : 0) - (lag_rem_valid ? 1 : 0);
+// Net deltas (computed from registered col_buf values — combinational in CMP)
+wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid_r ? $signed({1'b0, lead_add_val_r}) : 0)
+                                      - (lead_rem_valid_r ? $signed({1'b0, lead_rem_val_r}) : 0);
+wire signed [1:0] lead_cnt_delta = (lead_add_valid_r ? 1 : 0) - (lead_rem_valid_r ? 1 : 0);
+
+wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid_r ? $signed({1'b0, lag_add_val_r}) : 0)
+                                     - (lag_rem_valid_r ? $signed({1'b0, lag_rem_val_r}) : 0);
+wire signed [1:0] lag_cnt_delta = (lag_add_valid_r ? 1 : 0) - (lag_rem_valid_r ? 1 : 0);
 
 // ============================================================================
 // NOISE ESTIMATE COMPUTATION (combinational for CFAR mode selection)
@@ -267,7 +280,7 @@ always @(posedge clk or negedge reset_n) begin
         state          <= ST_IDLE;
         detect_flag    <= 1'b0;
         detect_valid   <= 1'b0;
-        detect_range   <= 6'd0;
+        detect_range   <= {ROW_BITS{1'b0}};
         detect_doppler <= 5'd0;
         detect_magnitude <= {MAG_WIDTH{1'b0}};
         detect_threshold <= {MAG_WIDTH{1'b0}};
@@ -288,6 +301,14 @@ always @(posedge clk or negedge reset_n) begin
         noise_sum_reg  <= 0;
         noise_product  <= 0;
         adaptive_thr   <= 0;
+        lead_add_val_r <= 0;
+        lead_rem_val_r <= 0;
+        lag_rem_val_r  <= 0;
+        lag_add_val_r  <= 0;
+        lead_add_valid_r <= 0;
+        lead_rem_valid_r <= 0;
+        lag_rem_valid_r  <= 0;
+        lag_add_valid_r  <= 0;
         r_guard        <= 4'd2;
         r_train        <= 5'd8;
         r_alpha        <= 8'h30;
@@ -364,7 +385,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (r_enable) begin
                     col_idx      <= 0;
                     col_load_idx <= 0;
-                    mag_raddr    <= {6'd0, 5'd0};
+                    mag_raddr    <= {{ROW_BITS{1'b0}}, 5'd0};
                     state        <= ST_COL_LOAD;
                 end else begin
                     state <= ST_DONE;
@@ -382,14 +403,14 @@ always @(posedge clk or negedge reset_n) begin
 
             if (col_load_idx == 0) begin
                 // First address already presented, advance to range=1
-                mag_raddr    <= {6'd1, col_idx};
+                mag_raddr    <= {{{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 col_load_idx <= 1;
             end else if (col_load_idx <= NUM_RANGE_BINS) begin
                 // Capture previous read
                 col_buf[col_load_idx - 1] <= mag_rdata;
 
                 if (col_load_idx < NUM_RANGE_BINS) begin
-                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + 6'd1, col_idx};
+                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + {{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 end
 
                 col_load_idx <= col_load_idx + 1;
@@ -441,6 +462,19 @@ always @(posedge clk or negedge reset_n) begin
             cfar_status <= {4'd4, 1'b0, col_idx[2:0]};
 
             noise_sum_reg <= noise_sum_comb;
+
+            // Pipeline: register col_buf reads for next CUT's window update.
+            // Indices depend only on cut_idx/r_guard/r_train (all stable here).
+            // Breaks the 9-level col_buf mux tree out of ST_CFAR_CMP.
+            lead_add_val_r   <= lead_add_val;
+            lead_rem_val_r   <= lead_rem_val;
+            lag_rem_val_r    <= lag_rem_val;
+            lag_add_val_r    <= lag_add_val;
+            lead_add_valid_r <= lead_add_valid;
+            lead_rem_valid_r <= lead_rem_valid;
+            lag_rem_valid_r  <= lag_rem_valid;
+            lag_add_valid_r  <= lag_add_valid;
+
             state <= ST_CFAR_MUL;
         end
 
@@ -513,7 +547,7 @@ always @(posedge clk or negedge reset_n) begin
             if (col_idx < NUM_DOPPLER_BINS - 1) begin
                 col_idx      <= col_idx + 1;
                 col_load_idx <= 0;
-                mag_raddr    <= {6'd0, col_idx + 5'd1};
+                mag_raddr    <= {{ROW_BITS{1'b0}}, col_idx + 5'd1};
                 state        <= ST_COL_LOAD;
             end else begin
                 state <= ST_DONE;

9_Firmware/9_2_FPGA/chirp_memory_loader_param.v

@@ -4,10 +4,6 @@ module chirp_memory_loader_param #(
     parameter LONG_Q_FILE_SEG0 = "long_chirp_seg0_q.mem",
     parameter LONG_I_FILE_SEG1 = "long_chirp_seg1_i.mem",
     parameter LONG_Q_FILE_SEG1 = "long_chirp_seg1_q.mem",
-    parameter LONG_I_FILE_SEG2 = "long_chirp_seg2_i.mem",
-    parameter LONG_Q_FILE_SEG2 = "long_chirp_seg2_q.mem",
-    parameter LONG_I_FILE_SEG3 = "long_chirp_seg3_i.mem",
-    parameter LONG_Q_FILE_SEG3 = "long_chirp_seg3_q.mem",
     parameter SHORT_I_FILE = "short_chirp_i.mem",
     parameter SHORT_Q_FILE = "short_chirp_q.mem",
     parameter DEBUG = 1
@@ -17,17 +13,17 @@ module chirp_memory_loader_param #(
     input wire [1:0] segment_select,
     input wire mem_request,
     input wire use_long_chirp,
-    input wire [9:0] sample_addr,
+    input wire [10:0] sample_addr,
     output reg [15:0] ref_i,
     output reg [15:0] ref_q,
     output reg mem_ready
 );
 
-// Memory declarations - now 4096 samples for 4 segments
+// Memory declarations — 2 long segments × 2048 = 4096 samples
 (* ram_style = "block" *) reg [15:0] long_chirp_i [0:4095];
 (* ram_style = "block" *) reg [15:0] long_chirp_q [0:4095];
-(* ram_style = "block" *) reg [15:0] short_chirp_i [0:1023];
-(* ram_style = "block" *) reg [15:0] short_chirp_q [0:1023];
+(* ram_style = "block" *) reg [15:0] short_chirp_i [0:2047];
+(* ram_style = "block" *) reg [15:0] short_chirp_q [0:2047];
 
 // Initialize memory
 integer i;
@@ -35,66 +31,47 @@ integer i;
 initial begin
     `ifdef SIMULATION
     if (DEBUG) begin
-        $display("[MEM] Starting memory initialization for 4 long chirp segments");
+        $display("[MEM] Starting memory initialization for 2 long chirp segments");
     end
     `endif
-    
-    // === LOAD LONG CHIRP - 4 SEGMENTS ===
-    // Segment 0 (addresses 0-1023)
-    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
-    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
+
+    // === LOAD LONG CHIRP — 2 SEGMENTS ===
+    // Segment 0 (addresses 0-2047)
+    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 2047);
+    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 2047);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-2047)");
     `endif
-    
-    // Segment 1 (addresses 1024-2047)
-    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
-    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
+
+    // Segment 1 (addresses 2048-4095)
+    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 2048, 4095);
+    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 2048, 4095);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (2048-4095)");
     `endif
-    
-    // Segment 2 (addresses 2048-3071)
-    $readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
-    $readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
-    `endif
-    
-    // Segment 3 (addresses 3072-4095)
-    $readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
-    $readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
-    `endif
-    
+
     // === LOAD SHORT CHIRP ===
-    // Load first 50 samples (0-49). Explicit range prevents iverilog warning
-    // about insufficient words for the full [0:1023] array.
+    // Load first 50 samples (0-49)
     $readmemh(SHORT_I_FILE, short_chirp_i, 0, 49);
     $readmemh(SHORT_Q_FILE, short_chirp_q, 0, 49);
     `ifdef SIMULATION
     if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
     `endif
-    
-    // Zero pad remaining 974 samples (50-1023)
-    for (i = 50; i < 1024; i = i + 1) begin
+
+    // Zero pad remaining samples (50-2047)
+    for (i = 50; i < 2048; i = i + 1) begin
         short_chirp_i[i] = 16'h0000;
         short_chirp_q[i] = 16'h0000;
     end
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
-    
+    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-2047");
+
     // === VERIFICATION ===
     if (DEBUG) begin
         $display("[MEM] Memory loading complete. Verification samples:");
         $display("  Long[0]:     I=%h Q=%h", long_chirp_i[0], long_chirp_q[0]);
-        $display("  Long[1023]:  I=%h Q=%h", long_chirp_i[1023], long_chirp_q[1023]);
-        $display("  Long[1024]:  I=%h Q=%h", long_chirp_i[1024], long_chirp_q[1024]);
         $display("  Long[2047]:  I=%h Q=%h", long_chirp_i[2047], long_chirp_q[2047]);
         $display("  Long[2048]:  I=%h Q=%h", long_chirp_i[2048], long_chirp_q[2048]);
-        $display("  Long[3071]:  I=%h Q=%h", long_chirp_i[3071], long_chirp_q[3071]);
-        $display("  Long[3072]:  I=%h Q=%h", long_chirp_i[3072], long_chirp_q[3072]);
         $display("  Long[4095]:  I=%h Q=%h", long_chirp_i[4095], long_chirp_q[4095]);
         $display("  Short[0]:    I=%h Q=%h", short_chirp_i[0], short_chirp_q[0]);
         $display("  Short[49]:   I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
@@ -104,8 +81,8 @@ initial begin
 end
 
 // Memory access logic
-// long_addr is combinational — segment_select[1:0] concatenated with sample_addr[9:0]
-wire [11:0] long_addr = {segment_select, sample_addr};
+// long_addr: segment_select[0] selects segment (0 or 1), sample_addr[10:0] selects within
+wire [11:0] long_addr = {segment_select[0], sample_addr};
 
 // ---- BRAM read block (sync-only, sync reset) ----
 // REQP-1839/1840 fix: BRAM output registers cannot have async resets.
@@ -119,7 +96,7 @@ always @(posedge clk) begin
         if (use_long_chirp) begin
             ref_i <= long_chirp_i[long_addr];
             ref_q <= long_chirp_q[long_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Long chirp: seg=%b, addr=%d, I=%h, Q=%h",
@@ -128,10 +105,10 @@ always @(posedge clk) begin
             end
             `endif
         end else begin
-            // Short chirp (0-1023)
+            // Short chirp (0-2047)
             ref_i <= short_chirp_i[sample_addr];
             ref_q <= short_chirp_q[sample_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Short chirp: addr=%d, I=%h, Q=%h",
@@ -151,4 +128,4 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/doppler_processor.v

@@ -32,13 +32,15 @@
 //     w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
 // ============================================================================
 
+`include "radar_params.vh"
+
 module doppler_processor_optimized #(
-    parameter DOPPLER_FFT_SIZE   = 16,     // FFT size per sub-frame (was 32)
-    parameter RANGE_BINS         = 64,
-    parameter CHIRPS_PER_FRAME   = 32,     // Total chirps in frame (16+16)
-    parameter CHIRPS_PER_SUBFRAME = 16,    // Chirps per sub-frame
+    parameter DOPPLER_FFT_SIZE   = `RP_DOPPLER_FFT_SIZE,    // 16
+    parameter RANGE_BINS         = `RP_NUM_RANGE_BINS,      // 512
+    parameter CHIRPS_PER_FRAME   = `RP_CHIRPS_PER_FRAME,    // 32
+    parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
     parameter WINDOW_TYPE        = 0,      // 0=Hamming, 1=Rectangular
-    parameter DATA_WIDTH         = 16
+    parameter DATA_WIDTH         = `RP_DATA_WIDTH           // 16
 )(
     input wire clk,
     input wire reset_n,
@@ -48,7 +50,7 @@ module doppler_processor_optimized #(
     output reg [31:0] doppler_output,
     output reg doppler_valid,
     output reg [4:0] doppler_bin,      // {sub_frame, bin[3:0]}
-    output reg [5:0] range_bin,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
     output reg sub_frame,              // 0=long PRI, 1=short PRI
     output wire processing_active,
     output wire frame_complete,
@@ -57,16 +59,16 @@ module doppler_processor_optimized #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [10:0] fv_mem_write_addr,
-    output wire [10:0] fv_mem_read_addr,
-    output wire [5:0]  fv_write_range_bin,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_write_range_bin,
     output wire [4:0]  fv_write_chirp_index,
-    output wire [5:0]  fv_read_range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_read_range_bin,
     output wire [4:0]  fv_read_doppler_index,
     output wire [9:0]  fv_processing_timeout,
     output wire        fv_frame_buffer_full,
     output wire        fv_mem_we,
-    output wire [10:0] fv_mem_waddr_r
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_waddr_r
 `endif
 );
 
@@ -115,9 +117,9 @@ localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
 // ==============================================
 // Control Registers
 // ==============================================
-reg [5:0] write_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] write_range_bin;
 reg [4:0] write_chirp_index;
-reg [5:0] read_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] read_range_bin;
 reg [4:0] read_doppler_index;
 reg frame_buffer_full;
 reg [9:0] chirps_received;
@@ -147,8 +149,8 @@ wire fft_output_last;
 // ==============================================
 // Addressing
 // ==============================================
-wire [10:0] mem_write_addr;
-wire [10:0] mem_read_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_write_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_read_addr;
 
 assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
 assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
@@ -180,7 +182,7 @@ reg [9:0] processing_timeout;
 
 // Memory write enable and data signals
 reg mem_we;
-reg [10:0] mem_waddr_r;
+reg [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_waddr_r;
 reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
 
 // Memory read data
@@ -531,6 +533,11 @@ xfft_16 fft_inst (
 // Status Outputs
 // ==============================================
 assign processing_active = (state != S_IDLE);
+// NOTE: frame_complete is a LEVEL, not a pulse. It is high whenever the
+// doppler processor is idle with no buffered frame. radar_receiver_final.v
+// converts this to a single-cycle rising-edge pulse before routing to
+// downstream consumers (USB FT2232H, AGC, CFAR). Do NOT connect this
+// level output directly to modules that expect a pulse.
 assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
 
 endmodule

9_Firmware/9_2_FPGA/fft_engine.v

@@ -28,13 +28,16 @@
  * Clock domain: single clock (clk), active-low async reset (reset_n).
  */
 
+// Include single source of truth for default parameters
+`include "radar_params.vh"
+
 module fft_engine #(
-    parameter N            = 1024,
-    parameter LOG2N        = 10,
+    parameter N            = `RP_FFT_SIZE,       // 2048
+    parameter LOG2N        = `RP_LOG2_FFT_SIZE,  // 11
     parameter DATA_W       = 16,
     parameter INTERNAL_W   = 32,
     parameter TWIDDLE_W    = 16,
-    parameter TWIDDLE_FILE = "fft_twiddle_1024.mem"
+    parameter TWIDDLE_FILE = "fft_twiddle_2048.mem"
 )(
     input wire clk,
     input wire reset_n,

9_Firmware/9_2_FPGA/fft_twiddle_2048.mem

@@ -0,0 +1,515 @@
+// Quarter-wave cosine ROM for 2048-point FFT
+// 512 entries, 16-bit signed Q15 ($readmemh format)
+// cos(2*pi*k/2048) for k = 0..511
+7FFF
+7FFF
+7FFE
+7FFE
+7FFD
+7FFB
+7FF9
+7FF7
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9_Firmware/9_2_FPGA/matched_filter_multi_segment.v

@@ -1,5 +1,8 @@
 `timescale 1ns / 1ps
 // matched_filter_multi_segment.v
+
+`include "radar_params.vh"
+
 module matched_filter_multi_segment (
     input wire clk,           // 100MHz
     input wire reset_n,
@@ -18,14 +21,13 @@ module matched_filter_multi_segment (
     input wire mc_new_elevation,    // Toggle for new elevation (32)
     input wire mc_new_azimuth,      // Toggle for new azimuth (50)
     
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Reference chirp (upstream memory loader selects long/short via use_long_chirp)
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
     
     // Memory system interface
     output reg [1:0] segment_request,
-    output wire [9:0] sample_addr_out,  // Tell memory which sample we need
+    output wire [10:0] sample_addr_out,  // Tell memory which sample we need (11-bit for 2048)
     output reg mem_request,
     input wire mem_ready,
     
@@ -39,18 +41,18 @@ module matched_filter_multi_segment (
 );
 
 // ========== FIXED PARAMETERS ==========
-parameter BUFFER_SIZE = 1024;
-parameter LONG_CHIRP_SAMPLES = 3000;  // Still 3000 samples total
-parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5<EFBFBD>s @ 100MHz
-parameter OVERLAP_SAMPLES = 128;      // Standard for 1024-pt FFT
-parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES;  // 896 samples
-parameter DEBUG = 1;                  // Debug output control
+parameter BUFFER_SIZE = `RP_FFT_SIZE;              // 2048
+parameter LONG_CHIRP_SAMPLES = 3000;               // Still 3000 samples total
+parameter SHORT_CHIRP_SAMPLES = 50;                // 0.5 us @ 100MHz
+parameter OVERLAP_SAMPLES = `RP_OVERLAP_SAMPLES;   // 128
+parameter SEGMENT_ADVANCE = `RP_SEGMENT_ADVANCE;   // 2048 - 128 = 1920 samples
+parameter DEBUG = 1;                               // Debug output control
 
 // Calculate segments needed with overlap
-// For 3072 samples with 128 overlap: 
-// Segments = ceil((3072 - 128) / 896) = ceil(2944/896) = 4
-parameter LONG_SEGMENTS = 4;          // Now exactly 4 segments!
-parameter SHORT_SEGMENTS = 1;         // 50 samples padded to 1024
+// For 3000 samples with 128 overlap:
+// Segments = ceil((3000 - 2048) / 1920) + 1 = ceil(952/1920) + 1 = 2
+parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM;   // 2 segments
+parameter SHORT_SEGMENTS = 1;                      // 50 samples padded to 2048
 
 // ========== FIXED INTERNAL SIGNALS ==========
 reg signed [31:0] pc_i, pc_q;
@@ -59,19 +61,19 @@ reg pc_valid;
 // Dual buffer for overlap-save — BRAM inferred for synthesis
 (* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:BUFFER_SIZE-1];
 (* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:BUFFER_SIZE-1];
-reg [10:0] buffer_write_ptr;
-reg [10:0] buffer_read_ptr;
+reg [11:0] buffer_write_ptr;    // 12-bit for 0..2048
+reg [11:0] buffer_read_ptr;     // 12-bit for 0..2048
 reg buffer_has_data;
 reg buffer_processing;
 reg [15:0] chirp_samples_collected;
 
 // BRAM write port signals
 reg        buf_we;
-reg [9:0]  buf_waddr;
+reg [10:0] buf_waddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_wdata_i, buf_wdata_q;
 
 // BRAM read port signals
-reg [9:0]  buf_raddr;
+reg [10:0] buf_raddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_rdata_i, buf_rdata_q;
 
 // State machine
@@ -94,15 +96,22 @@ reg chirp_complete;
 reg saw_chain_output;             // Flag: chain started producing output
 
 // Overlap cache — captured during ST_PROCESSING, written back in ST_OVERLAP_COPY
+// Uses sync-only write block to allow distributed RAM inference (not FFs).
+// 128 entries = distributed RAM (LUTRAM), NOT BRAM (too shallow).
 reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
 reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
 reg [7:0] overlap_copy_count;
 
+// Overlap cache write port signals (driven from FSM, used in sync-only block)
+reg        ov_we;
+reg [6:0]  ov_waddr;
+reg signed [15:0] ov_wdata_i, ov_wdata_q;
+
 // Microcontroller sync detection
 reg mc_new_chirp_prev, mc_new_elevation_prev, mc_new_azimuth_prev;
-wire chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev;
-wire elevation_change_pulse = mc_new_elevation && !mc_new_elevation_prev;
-wire azimuth_change_pulse = mc_new_azimuth && !mc_new_azimuth_prev;
+wire chirp_start_pulse = mc_new_chirp ^ mc_new_chirp_prev;           // Toggle-to-pulse (any edge)
+wire elevation_change_pulse = mc_new_elevation ^ mc_new_elevation_prev; // Toggle-to-pulse
+wire azimuth_change_pulse = mc_new_azimuth ^ mc_new_azimuth_prev;     // Toggle-to-pulse
 
 // Processing chain signals
 wire [15:0] fft_pc_i, fft_pc_q;
@@ -115,7 +124,7 @@ reg fft_input_valid;
 reg fft_start;
 
 // ========== SAMPLE ADDRESS OUTPUT ==========
-assign sample_addr_out = buffer_read_ptr;
+assign sample_addr_out = buffer_read_ptr[10:0];
 
 // ========== MICROCONTROLLER SYNC ==========
 always @(posedge clk or negedge reset_n) begin
@@ -152,6 +161,16 @@ always @(posedge clk) begin
     end
 end
 
+// ========== OVERLAP CACHE WRITE PORT (sync only — distributed RAM inference) ==========
+// Removing async reset from memory write path prevents Vivado from
+// synthesizing the 128x16 arrays as FFs + mux trees.
+always @(posedge clk) begin
+    if (ov_we) begin
+        overlap_cache_i[ov_waddr] <= ov_wdata_i;
+        overlap_cache_q[ov_waddr] <= ov_wdata_q;
+    end
+end
+
 // ========== BRAM READ PORT (synchronous, no async reset) ==========
 always @(posedge clk) begin
     buf_rdata_i <= input_buffer_i[buf_raddr];
@@ -183,12 +202,17 @@ always @(posedge clk or negedge reset_n) begin
         buf_wdata_i <= 0;
         buf_wdata_q <= 0;
         buf_raddr <= 0;
+        ov_we <= 0;
+        ov_waddr <= 0;
+        ov_wdata_i <= 0;
+        ov_wdata_q <= 0;
         overlap_copy_count <= 0;
     end else begin
         pc_valid <= 0;
         mem_request <= 0;
         fft_input_valid <= 0;
         buf_we <= 0;  // Default: no write
+        ov_we <= 0;   // Default: no overlap write
         
         case (state)
             ST_IDLE: begin
@@ -223,7 +247,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
                     // Store in buffer via BRAM write port
                     buf_we <= 1;
-                    buf_waddr <= buffer_write_ptr[9:0];
+                    buf_waddr <= buffer_write_ptr[10:0];
                     buf_wdata_i <= ddc_i[17:2] + ddc_i[1];
                     buf_wdata_q <= ddc_q[17:2] + ddc_q[1];
                     
@@ -244,6 +268,7 @@ always @(posedge clk or negedge reset_n) begin
                     if (!use_long_chirp) begin
                         if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                             state <= ST_ZERO_PAD;
+                            chirp_complete <= 1;  // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
                             `ifdef SIMULATION
                             $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                      chirp_samples_collected + 1);
@@ -257,8 +282,8 @@ always @(posedge clk or negedge reset_n) begin
                 // missing the transition when buffer_write_ptr updates via
                 // non-blocking assignment one cycle after the last write.
                 //
-                // Overlap-save fix: fill the FULL 1024-sample buffer before
-                // processing.  For segment 0 this means 1024 fresh samples.
+                // Overlap-save fix: fill the FULL FFT_SIZE-sample buffer before
+                // processing.  For segment 0 this means FFT_SIZE fresh samples.
                 // For segments 1+, write_ptr starts at OVERLAP_SAMPLES (128)
                 // so we collect 896 new samples to fill the buffer.
                 if (use_long_chirp) begin
@@ -295,7 +320,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_ZERO_PAD: begin
                 // Zero-pad remaining buffer via BRAM write port
                 buf_we <= 1;
-                buf_waddr <= buffer_write_ptr[9:0];
+                buf_waddr <= buffer_write_ptr[10:0];
                 buf_wdata_i <= 16'd0;
                 buf_wdata_q <= 16'd0;
                 buffer_write_ptr <= buffer_write_ptr + 1;
@@ -315,7 +340,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_REF: begin
                 // Wait for memory to provide reference coefficients
-                buf_raddr <= 10'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
+                buf_raddr <= 11'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
                 if (mem_ready) begin
                     // Start processing — buf_rdata[0] will be valid on FIRST clock of ST_PROCESSING
                     buffer_processing <= 1;
@@ -344,10 +369,12 @@ always @(posedge clk or negedge reset_n) begin
                     // 2. Request corresponding reference sample
                     mem_request <= 1'b1;
                     
-                    // 3. Cache tail samples for overlap-save
+                    // 3. Cache tail samples for overlap-save (via sync-only write port)
                     if (buffer_read_ptr >= SEGMENT_ADVANCE) begin
-                        overlap_cache_i[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_i;
-                        overlap_cache_q[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_q;
+                        ov_we <= 1;
+                        ov_waddr <= buffer_read_ptr - SEGMENT_ADVANCE;  // 0..OVERLAP-1
+                        ov_wdata_i <= buf_rdata_i;
+                        ov_wdata_q <= buf_rdata_q;
                     end
                     
                     // Debug every 100 samples
@@ -361,7 +388,7 @@ always @(posedge clk or negedge reset_n) begin
                     end
                     
                     // Present NEXT read address (for next cycle)
-                    buf_raddr <= buffer_read_ptr[9:0] + 10'd1;
+                    buf_raddr <= buffer_read_ptr[10:0] + 11'd1;
                     buffer_read_ptr <= buffer_read_ptr + 1;
                     
                 end else if (buffer_read_ptr >= BUFFER_SIZE) begin
@@ -382,7 +409,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_FFT: begin
                 // Wait for the processing chain to complete ALL outputs.
-                // The chain streams 1024 samples (fft_pc_valid=1 for 1024 clocks),
+                // The chain streams FFT_SIZE samples (fft_pc_valid=1 for FFT_SIZE clocks),
                 // then transitions to ST_DONE (9) -> ST_IDLE (0).
                 // We track when output starts (saw_chain_output) and only
                 // proceed once the chain returns to idle after outputting.
@@ -454,7 +481,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_OVERLAP_COPY: begin
                 // Write one cached overlap sample per cycle to BRAM
                 buf_we <= 1;
-                buf_waddr <= {{2{1'b0}}, overlap_copy_count};
+                buf_waddr <= {{3{1'b0}}, overlap_copy_count};
                 buf_wdata_i <= overlap_cache_i[overlap_copy_count];
                 buf_wdata_q <= overlap_cache_q[overlap_copy_count];
                 
@@ -500,11 +527,9 @@ matched_filter_processing_chain m_f_p_c(
     // Chirp Selection
     .chirp_counter(chirp_counter),
     
-    // Reference Chirp Memory Interfaces
-    .long_chirp_real(long_chirp_real),
-    .long_chirp_imag(long_chirp_imag),
-    .short_chirp_real(short_chirp_real),
-    .short_chirp_imag(short_chirp_imag),
+    // Reference Chirp Memory Interface (single pair — upstream selects long/short)
+    .ref_chirp_real(ref_chirp_real),
+    .ref_chirp_imag(ref_chirp_imag),
     
     // Output
     .range_profile_i(fft_pc_i),

9_Firmware/9_2_FPGA/matched_filter_processing_chain.v

@@ -15,26 +15,28 @@
  *   .clk, .reset_n
  *   .adc_data_i, .adc_data_q, .adc_valid      <- from input buffer
  *   .chirp_counter                              <- 6-bit frame counter
- *   .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
+ *   .ref_chirp_real/imag                     <- reference (time-domain)
  *   .range_profile_i, .range_profile_q, .range_profile_valid -> output
  *   .chain_state                                -> 4-bit status
  *
  * Clock domain: clk (100 MHz system clock)
  * Data format:  16-bit signed (Q15 fixed-point)
- * FFT size:     1024 points
+ * FFT size:     2048 points (parameterized via radar_params.vh)
  *
  * Pipeline states:
- *   IDLE -> FWD_FFT (collect 1024 samples + bit-reverse copy)
+ *   IDLE -> FWD_FFT (collect 2048 samples + bit-reverse copy)
  *        -> FWD_BUTTERFLY (forward FFT of signal)
  *        -> REF_BITREV (bit-reverse copy reference into work arrays)
  *        -> REF_BUTTERFLY (forward FFT of reference)
  *        -> MULTIPLY (conjugate multiply in freq domain)
  *        -> INV_BITREV (bit-reverse copy product)
  *        -> INV_BUTTERFLY (inverse FFT + 1/N scaling)
- *        -> OUTPUT (stream 1024 samples)
+ *        -> OUTPUT (stream 2048 samples)
  *        -> DONE -> IDLE
  */
 
+`include "radar_params.vh"
+
 module matched_filter_processing_chain (
     input wire clk,
     input wire reset_n,
@@ -48,10 +50,10 @@ module matched_filter_processing_chain (
     input wire [5:0] chirp_counter,
 
     // Reference chirp (time-domain, latency-aligned by upstream buffer)
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Upstream chirp_memory_loader_param selects long/short reference
+    // via use_long_chirp — this single pair carries whichever is active.
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
 
     // Output: range profile (pulse-compressed)
     output wire signed [15:0] range_profile_i,
@@ -66,8 +68,8 @@ module matched_filter_processing_chain (
 // ============================================================================
 // PARAMETERS
 // ============================================================================
-localparam FFT_SIZE   = 1024;
-localparam ADDR_BITS  = 10;    // log2(1024)
+localparam FFT_SIZE   = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS  = `RP_LOG2_FFT_SIZE; // log2(2048) = 11
 
 // State encoding (4-bit, up to 16 states)
 localparam [3:0] ST_IDLE           = 4'd0;
@@ -87,8 +89,8 @@ reg [3:0] state;
 // SIGNAL BUFFERS
 // ============================================================================
 // Input sample counter
-reg [ADDR_BITS:0] fwd_in_count;     // 0..1024
-reg fwd_frame_done;                  // All 1024 samples received
+reg [ADDR_BITS:0] fwd_in_count;     // 0..FFT_SIZE
+reg fwd_frame_done;                  // All FFT_SIZE samples received
 
 // Signal time-domain buffer
 reg signed [15:0] fwd_buf_i [0:FFT_SIZE-1];
@@ -175,7 +177,7 @@ always @(posedge clk or negedge reset_n) begin
 
         case (state)
         // ================================================================
-        // IDLE: Wait for valid ADC data, start collecting 1024 samples
+        // IDLE: Wait for valid ADC data, start collecting 2048 samples
         // ================================================================
         ST_IDLE: begin
             fwd_in_count   <= 0;
@@ -189,8 +191,8 @@ always @(posedge clk or negedge reset_n) begin
                 // Store first sample (signal + reference)
                 fwd_buf_i[0] <= $signed(adc_data_i);
                 fwd_buf_q[0] <= $signed(adc_data_q);
-                ref_buf_i[0] <= $signed(long_chirp_real);
-                ref_buf_q[0] <= $signed(long_chirp_imag);
+                ref_buf_i[0] <= $signed(ref_chirp_real);
+                ref_buf_q[0] <= $signed(ref_chirp_imag);
                 fwd_in_count <= 1;
                 state        <= ST_FWD_FFT;
             end
@@ -198,6 +200,7 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // FWD_FFT: Collect remaining samples, then bit-reverse copy signal
+        // (2048 samples total)
         // ================================================================
         ST_FWD_FFT: begin
             if (!fwd_frame_done) begin
@@ -205,8 +208,8 @@ always @(posedge clk or negedge reset_n) begin
                 if (adc_valid && fwd_in_count < FFT_SIZE) begin
                     fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
                     fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
-                    ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
-                    ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
+                    ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
+                    ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
                     fwd_in_count <= fwd_in_count + 1;
                 end
 
@@ -437,7 +440,7 @@ always @(posedge clk or negedge reset_n) begin
                 end
             end
 
-            // Scale by 1/N (right shift by log2(1024) = 10) and store
+            // Scale by 1/N (right shift by log2(2048) = 11) and store
             for (i = 0; i < FFT_SIZE; i = i + 1) begin : ifft_scale
                 reg signed [31:0] scaled_re, scaled_im;
                 scaled_re = work_re[i] >>> ADDR_BITS;
@@ -467,7 +470,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream out 1024 range profile samples, one per clock
+        // OUTPUT: Stream out 2048 range profile samples, one per clock
         // ================================================================
         ST_OUTPUT: begin
             if (out_count < FFT_SIZE) begin
@@ -531,16 +534,16 @@ end
 // ============================================================================
 // SYNTHESIS IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
 // ============================================================================
-// Uses a single fft_engine instance (1024-pt) reused 3 times:
+// Uses a single fft_engine instance (2048-pt) reused 3 times:
 //   1. Forward FFT of signal
 //   2. Forward FFT of reference
 //   3. Inverse FFT of conjugate product
 // Conjugate multiply done via frequency_matched_filter (4-stage pipeline).
 //
 // Buffer scheme (BRAM-inferrable):
-//   sig_buf[1024]:  ADC input -> signal FFT output
-//   ref_buf[1024]:  Reference input -> reference FFT output
-//   prod_buf[1024]: Conjugate multiply output -> IFFT output
+//   sig_buf[2048]:  ADC input -> signal FFT output
+//   ref_buf[2048]:  Reference input -> reference FFT output
+//   prod_buf[2048]: Conjugate multiply output -> IFFT output
 //
 // Memory access is INSIDE always @(posedge clk) blocks (no async reset)
 // using local blocking variables. This eliminates NBA race conditions
@@ -552,12 +555,12 @@ end
 //   out_primed   — for output streaming
 // ============================================================================
 
-localparam FFT_SIZE  = 1024;
-localparam ADDR_BITS = 10;
+localparam FFT_SIZE  = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS = `RP_LOG2_FFT_SIZE; // 11
 
 // State encoding
 localparam [3:0] ST_IDLE     = 4'd0,
-                 ST_COLLECT  = 4'd1,   // Collect 1024 ADC + ref samples
+                 ST_COLLECT  = 4'd1,   // Collect FFT_SIZE ADC + ref samples
                  ST_SIG_FFT  = 4'd2,   // Forward FFT of signal
                  ST_SIG_CAP  = 4'd3,   // Capture signal FFT output
                  ST_REF_FFT  = 4'd4,   // Forward FFT of reference
@@ -565,7 +568,7 @@ localparam [3:0] ST_IDLE     = 4'd0,
                  ST_MULTIPLY = 4'd6,   // Conjugate multiply (pipelined)
                  ST_INV_FFT  = 4'd7,   // Inverse FFT of product
                  ST_INV_CAP  = 4'd8,   // Capture IFFT output
-                 ST_OUTPUT   = 4'd9,   // Stream 1024 results
+                 ST_OUTPUT   = 4'd9,   // Stream FFT_SIZE results
                  ST_DONE     = 4'd10;
 
 reg [3:0] state;
@@ -588,11 +591,11 @@ reg signed [15:0] prod_rdata_i, prod_rdata_q;
 // ============================================================================
 // COUNTERS
 // ============================================================================
-reg [ADDR_BITS:0] collect_count;   // 0..1024 for sample collection
-reg [ADDR_BITS:0] feed_count;      // 0..1024 for feeding FFT engine
-reg [ADDR_BITS:0] cap_count;       // 0..1024 for capturing FFT output
-reg [ADDR_BITS:0] mult_count;      // 0..1024 for multiply feeding
-reg [ADDR_BITS:0] out_count;       // 0..1024 for output streaming
+reg [ADDR_BITS:0] collect_count;   // 0..FFT_SIZE for sample collection
+reg [ADDR_BITS:0] feed_count;      // 0..FFT_SIZE for feeding FFT engine
+reg [ADDR_BITS:0] cap_count;       // 0..FFT_SIZE for capturing FFT output
+reg [ADDR_BITS:0] mult_count;      // 0..FFT_SIZE for multiply feeding
+reg [ADDR_BITS:0] out_count;       // 0..FFT_SIZE for output streaming
 
 // BRAM read latency pipeline flags
 reg feed_primed;   // 1 = BRAM rdata valid for feed operations
@@ -617,7 +620,7 @@ fft_engine #(
     .DATA_W(16),
     .INTERNAL_W(32),
     .TWIDDLE_W(16),
-    .TWIDDLE_FILE("fft_twiddle_1024.mem")
+    .TWIDDLE_FILE("fft_twiddle_2048.mem")
 ) fft_inst (
     .clk(clk),
     .reset_n(reset_n),
@@ -775,16 +778,16 @@ always @(posedge clk) begin : ref_bram_port
         if (adc_valid) begin
             we      = 1'b1;
             addr    = 0;
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_COLLECT: begin
         if (adc_valid && collect_count < FFT_SIZE) begin
             we      = 1'b1;
             addr    = collect_count[ADDR_BITS-1:0];
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_REF_FFT: begin
@@ -968,7 +971,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // COLLECT: Gather 1024 ADC + reference samples
+        // COLLECT: Gather 2048 ADC + reference samples
         // Writes happen in sig/ref BRAM ports (they see state==ST_COLLECT)
         // ================================================================
         ST_COLLECT: begin
@@ -977,7 +980,7 @@ always @(posedge clk or negedge reset_n) begin
             end
 
             if (collect_count == FFT_SIZE) begin
-                // All 1024 samples collected — start signal FFT
+                // All 2048 samples collected — start signal FFT
                 state       <= ST_SIG_FFT;
                 fft_start   <= 1'b1;
                 fft_inverse <= 1'b0;  // Forward FFT
@@ -1091,7 +1094,7 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MULTIPLY: Stream sig FFT and ref FFT through freq_matched_filter
         // Both sig_buf and ref_buf are read simultaneously (separate BRAM
-        // ports). Pipeline latency = 4 clocks. Feed 1024 pairs, then flush.
+        // ports). Pipeline latency = 4 clocks. Feed 2048 pairs, then flush.
         // ================================================================
         ST_MULTIPLY: begin
             if (mult_count < FFT_SIZE) begin
@@ -1180,7 +1183,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream 1024 range profile samples
+        // OUTPUT: Stream 2048 range profile samples
         // BRAM read latency: present address, data valid next cycle.
         // ================================================================
         ST_OUTPUT: begin

9_Firmware/9_2_FPGA/radar_mode_controller.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 /**
  * radar_mode_controller.v
  *
@@ -18,12 +20,18 @@
  *   - 32 chirps per elevation
  *   - 31 elevations per azimuth
  *   - 50 azimuths per full scan
- *   - Each chirp: Long chirp → Listen → Guard → Short chirp → Listen
  *
- * Modes of operation:
+ * Chirp sequence depends on range_mode (host_range_mode, opcode 0x20):
+ *   range_mode 2'b00 (3 km):  All short chirps only. Long chirp blind zone
+ *     (4500 m) exceeds 3 km max range, so long chirps are useless.
+ *   range_mode 2'b01 (long-range): Dual chirp — Long chirp → Listen → Guard
+ *     → Short chirp → Listen. First half of chirps_per_elev are long, second
+ *     half are short (blind-zone fill).
+ *
+ * Modes of operation (host_radar_mode, opcode 0x01):
  *   mode[1:0]:
  *     2'b00 = STM32-driven (pass through stm32 toggle signals)
- *     2'b01 = Free-running auto-scan (internal timing)
+ *     2'b01 = Free-running auto-scan (internal timing, short chirps only)
  *     2'b10 = Single-chirp (fire one chirp per trigger, for debug)
  *     2'b11 = Reserved
  *
@@ -31,9 +39,9 @@
  */
 
 module radar_mode_controller #(
-    parameter CHIRPS_PER_ELEVATION = 32,
+    parameter CHIRPS_PER_ELEVATION  = `RP_DEF_CHIRPS_PER_ELEV,
     parameter ELEVATIONS_PER_AZIMUTH = 31,
-    parameter AZIMUTHS_PER_SCAN = 50,
+    parameter AZIMUTHS_PER_SCAN     = 50,
 
     // Timing in 100 MHz clock cycles
     // Long chirp: 30us = 3000 cycles at 100 MHz
@@ -41,18 +49,24 @@ module radar_mode_controller #(
     // Guard: 175.4us = 17540 cycles
     // Short chirp: 0.5us = 50 cycles
     // Short listen: 174.5us = 17450 cycles
-    parameter LONG_CHIRP_CYCLES   = 3000,
-    parameter LONG_LISTEN_CYCLES  = 13700,
-    parameter GUARD_CYCLES        = 17540,
-    parameter SHORT_CHIRP_CYCLES  = 50,
-    parameter SHORT_LISTEN_CYCLES = 17450
+    parameter LONG_CHIRP_CYCLES   = `RP_DEF_LONG_CHIRP_CYCLES,
+    parameter LONG_LISTEN_CYCLES  = `RP_DEF_LONG_LISTEN_CYCLES,
+    parameter GUARD_CYCLES        = `RP_DEF_GUARD_CYCLES,
+    parameter SHORT_CHIRP_CYCLES  = `RP_DEF_SHORT_CHIRP_CYCLES,
+    parameter SHORT_LISTEN_CYCLES = `RP_DEF_SHORT_LISTEN_CYCLES
 ) (
     input wire clk,
     input wire reset_n,
 
-    // Mode selection
+    // Mode selection (host_radar_mode, opcode 0x01)
     input wire [1:0] mode,          // 00=STM32, 01=auto, 10=single, 11=rsvd
 
+    // Range mode (host_range_mode, opcode 0x20)
+    // Determines chirp type selection in pass-through and auto-scan modes.
+    //   2'b00 = 3 km  (all short chirps — long blind zone > max range)
+    //   2'b01 = Long-range (dual chirp: first half long, second half short)
+    input wire [1:0] range_mode,
+
     // STM32 pass-through inputs (active in mode 00)
     input wire stm32_new_chirp,
     input wire stm32_new_elevation,
@@ -61,10 +75,8 @@ module radar_mode_controller #(
     // Single-chirp trigger (active in mode 10)
     input wire trigger,
 
-    // Gap 2: Runtime-configurable timing inputs from host USB commands.
+    // Runtime-configurable timing inputs from host USB commands.
     // When connected, these override the compile-time parameters.
-    // When left at default (tied to parameter values at instantiation),
-    // behavior is identical to pre-Gap-2.
     input wire [15:0] cfg_long_chirp_cycles,
     input wire [15:0] cfg_long_listen_cycles,
     input wire [15:0] cfg_guard_cycles,
@@ -156,7 +168,7 @@ always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         scan_state      <= S_IDLE;
         timer           <= 18'd0;
-        use_long_chirp  <= 1'b1;
+        use_long_chirp  <= 1'b0;  // Default short chirp (safe for 3 km mode)
         mc_new_chirp    <= 1'b0;
         mc_new_elevation <= 1'b0;
         mc_new_azimuth  <= 1'b0;
@@ -172,7 +184,12 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 00: STM32-driven pass-through
         // The STM32 firmware controls timing; we just detect toggle edges
-        // and forward them to the receiver chain.
+        // and forward them to the receiver chain. Chirp type is determined
+        // by range_mode:
+        //   range_mode 00 (3 km):  ALL chirps are short (long blind zone
+        //     4500 m exceeds 3072 m max range, so long chirps are useless).
+        //   range_mode 01 (long-range): First half of chirps_per_elev are
+        //     long, second half are short (blind-zone fill).
         // ================================================================
         2'b00: begin
             // Reset auto-scan state
@@ -182,9 +199,29 @@ always @(posedge clk or negedge reset_n) begin
             // Pass through toggle signals
             if (stm32_chirp_toggle) begin
                 mc_new_chirp <= ~mc_new_chirp;  // Toggle output
-                use_long_chirp <= 1'b1;         // Default to long chirp
 
-                // Track chirp count (Gap 2: use runtime cfg_chirps_per_elev)
+                // Determine chirp type based on range_mode
+                case (range_mode)
+                `RP_RANGE_MODE_3KM: begin
+                    // 3 km mode: all short chirps
+                    use_long_chirp <= 1'b0;
+                end
+                `RP_RANGE_MODE_LONG: begin
+                    // Long-range: first half long, second half short.
+                    // chirps_per_elev is typically 32 (16 long + 16 short).
+                    // Use cfg_chirps_per_elev[5:1] as the halfway point.
+                    if (chirp_count < {1'b0, cfg_chirps_per_elev[5:1]})
+                        use_long_chirp <= 1'b1;
+                    else
+                        use_long_chirp <= 1'b0;
+                end
+                default: begin
+                    // Reserved modes: default to short chirp (safe)
+                    use_long_chirp <= 1'b0;
+                end
+                endcase
+
+                // Track chirp count
                 if (chirp_count < cfg_chirps_per_elev - 1)
                     chirp_count <= chirp_count + 1;
                 else
@@ -217,21 +254,33 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 01: Free-running auto-scan
         // Internally generates chirp timing matching the transmitter.
+        // For 3 km mode (range_mode 00): short chirps only. The long chirp
+        // blind zone (4500 m) exceeds the 3072 m max range, making long
+        // chirps useless. State machine skips S_LONG_CHIRP/LISTEN/GUARD.
+        // For long-range mode (range_mode 01): full dual-chirp sequence.
+        // NOTE: Auto-scan is primarily for bench testing without STM32.
         // ================================================================
         2'b01: begin
             case (scan_state)
             S_IDLE: begin
                 // Start first chirp immediately
-                scan_state     <= S_LONG_CHIRP;
-                timer          <= 18'd0;
-                use_long_chirp <= 1'b1;
-                mc_new_chirp   <= ~mc_new_chirp;  // Toggle to start chirp
-                chirp_count    <= 6'd0;
+                timer           <= 18'd0;
+                chirp_count     <= 6'd0;
                 elevation_count <= 6'd0;
-                azimuth_count  <= 6'd0;
+                azimuth_count   <= 6'd0;
+                mc_new_chirp    <= ~mc_new_chirp;  // Toggle to start chirp
+
+                // For 3 km mode, skip directly to short chirp
+                if (range_mode == `RP_RANGE_MODE_3KM) begin
+                    scan_state     <= S_SHORT_CHIRP;
+                    use_long_chirp <= 1'b0;
+                end else begin
+                    scan_state     <= S_LONG_CHIRP;
+                    use_long_chirp <= 1'b1;
+                end
 
                 `ifdef SIMULATION
-                $display("[MODE_CTRL] Auto-scan starting");
+                $display("[MODE_CTRL] Auto-scan starting, range_mode=%0d", range_mode);
                 `endif
             end
 
@@ -285,13 +334,19 @@ always @(posedge clk or negedge reset_n) begin
 
             S_ADVANCE: begin
                 // Advance chirp/elevation/azimuth counters
-                // (Gap 2: use runtime cfg_chirps_per_elev)
                 if (chirp_count < cfg_chirps_per_elev - 1) begin
                     // Next chirp in current elevation
                     chirp_count  <= chirp_count + 1;
                     mc_new_chirp <= ~mc_new_chirp;
-                    scan_state   <= S_LONG_CHIRP;
-                    use_long_chirp <= 1'b1;
+
+                    // For 3 km mode: short chirps only, skip long phases
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end else begin
                     chirp_count <= 6'd0;
 
@@ -300,8 +355,14 @@ always @(posedge clk or negedge reset_n) begin
                         elevation_count  <= elevation_count + 1;
                         mc_new_chirp     <= ~mc_new_chirp;
                         mc_new_elevation <= ~mc_new_elevation;
-                        scan_state       <= S_LONG_CHIRP;
-                        use_long_chirp   <= 1'b1;
+
+                        if (range_mode == `RP_RANGE_MODE_3KM) begin
+                            scan_state     <= S_SHORT_CHIRP;
+                            use_long_chirp <= 1'b0;
+                        end else begin
+                            scan_state     <= S_LONG_CHIRP;
+                            use_long_chirp <= 1'b1;
+                        end
                     end else begin
                         elevation_count <= 6'd0;
 
@@ -311,8 +372,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp     <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth   <= ~mc_new_azimuth;
-                            scan_state       <= S_LONG_CHIRP;
-                            use_long_chirp   <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
                         end else begin
                             // Full scan complete — restart
                             azimuth_count   <= 6'd0;
@@ -320,8 +387,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp    <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth  <= ~mc_new_azimuth;
-                            scan_state      <= S_LONG_CHIRP;
-                            use_long_chirp  <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
 
                             `ifdef SIMULATION
                             $display("[MODE_CTRL] Full scan complete, restarting");
@@ -337,16 +410,27 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // MODE 10: Single-chirp (debug mode)
-        // Fire one long chirp per trigger pulse, no scanning.
+        // Fire one chirp per trigger pulse, no scanning.
+        // Chirp type depends on range_mode:
+        //   3 km:  short chirp only
+        //   Long-range: long chirp (for testing long-chirp path)
         // ================================================================
         2'b10: begin
             case (scan_state)
             S_IDLE: begin
                 if (trigger_pulse) begin
-                    scan_state     <= S_LONG_CHIRP;
-                    timer          <= 18'd0;
-                    use_long_chirp <= 1'b1;
-                    mc_new_chirp   <= ~mc_new_chirp;
+                    timer        <= 18'd0;
+                    mc_new_chirp <= ~mc_new_chirp;
+
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        // 3 km: fire short chirp
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        // Long-range: fire long chirp
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end
             end
 
@@ -363,7 +447,27 @@ always @(posedge clk or negedge reset_n) begin
                 if (timer < cfg_long_listen_cycles - 1)
                     timer <= timer + 1;
                 else begin
-                    // Single chirp done, return to idle
+                    // Single long chirp done, return to idle
+                    timer      <= 18'd0;
+                    scan_state <= S_IDLE;
+                end
+            end
+
+            S_SHORT_CHIRP: begin
+                use_long_chirp <= 1'b0;
+                if (timer < cfg_short_chirp_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    timer <= 18'd0;
+                    scan_state <= S_SHORT_LISTEN;
+                end
+            end
+
+            S_SHORT_LISTEN: begin
+                if (timer < cfg_short_listen_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    // Single short chirp done, return to idle
                     timer      <= 18'd0;
                     scan_state <= S_IDLE;
                 end

9_Firmware/9_2_FPGA/radar_params.vh

@@ -0,0 +1,228 @@
+// ============================================================================
+// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
+// ============================================================================
+//
+// ALL modules in the FPGA processing chain MUST `include this file instead of
+// hardcoding range bins, segment counts, chirp samples, or timing values.
+//
+// This file uses `define macros (not localparam) so it can be included at any
+// scope. Each consuming module should include this file inside its body and
+// optionally alias macros to localparams for readability.
+//
+// BOARD VARIANTS:
+//   SUPPORT_LONG_RANGE = 0  (50T, USB_MODE=1)  — 3 km mode only
+//   SUPPORT_LONG_RANGE = 1  (200T, USB_MODE=0) — 3 km + 20 km modes
+//
+// RADAR MODES (runtime, via host_radar_mode register, opcode 0x01):
+//   2'b00 = STM32 pass-through (production — STM32 controls chirp timing)
+//   2'b01 = Auto-scan 3 km     (FPGA-timed, short chirps only)
+//   2'b10 = Single-chirp debug (one long chirp per trigger)
+//   2'b11 = Reserved / idle
+//
+// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
+//   2'b00 = 3 km   (default — pass-through treats all chirps as short)
+//   2'b01 = Long-range (pass-through: first half long, second half short)
+//   2'b10 = Reserved
+//   2'b11 = Reserved
+//
+// USAGE:
+//   `include "radar_params.vh"
+//   Then reference `RP_FFT_SIZE, `RP_NUM_RANGE_BINS, etc.
+//
+// PHYSICAL CONSTANTS (derived from hardware):
+//   ADC clock:           400 MSPS
+//   CIC decimation:      4x
+//   Processing rate:     100 MSPS (post-DDC)
+//   Range per sample:    c / (2 * 100e6) = 1.5 m
+//   FFT size:            2048
+//   Decimation factor:   4  (2048 FFT bins -> 512 output range bins)
+//   Range per dec. bin:  1.5 m * 4 = 6.0 m
+//   Max range (3 km):    512 * 6.0 = 3072 m
+//   Carrier frequency:   10.5 GHz
+//   IF frequency:        120 MHz
+//
+// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
+//   Range resolution:    c / (2 * BW)
+//     20 MHz -> 7.5 m
+//     30 MHz -> 5.0 m
+//   NOTE: Range resolution is independent of range-per-bin. Resolution
+//   determines the minimum separation between two targets; range-per-bin
+//   determines the spatial sampling grid.
+// ============================================================================
+
+`ifndef RADAR_PARAMS_VH
+`define RADAR_PARAMS_VH
+
+// ============================================================================
+// BOARD VARIANT — set at synthesis time, NOT runtime
+// ============================================================================
+// Default to 50T (conservative). Override in top-level or synthesis script:
+//   +define+SUPPORT_LONG_RANGE
+// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
+
+// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
+// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
+// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
+
+// ============================================================================
+// FFT AND PROCESSING CONSTANTS (fixed, both modes)
+// ============================================================================
+
+`define RP_FFT_SIZE             2048    // Range FFT points per segment
+`define RP_LOG2_FFT_SIZE        11      // log2(2048)
+`define RP_OVERLAP_SAMPLES      128     // Overlap between adjacent segments
+`define RP_SEGMENT_ADVANCE      1920    // FFT_SIZE - OVERLAP = 2048 - 128
+`define RP_DECIMATION_FACTOR    4       // Range bin decimation (2048 -> 512)
+`define RP_NUM_RANGE_BINS       512     // FFT_SIZE / DECIMATION_FACTOR
+`define RP_RANGE_BIN_BITS       9       // ceil(log2(512))
+`define RP_DOPPLER_FFT_SIZE     16      // Per sub-frame Doppler FFT
+`define RP_CHIRPS_PER_FRAME     32      // Total chirps (16 long + 16 short)
+`define RP_CHIRPS_PER_SUBFRAME  16      // Chirps per Doppler sub-frame
+`define RP_NUM_DOPPLER_BINS     32      // 2 sub-frames * 16 = 32
+`define RP_DATA_WIDTH           16      // ADC/processing data width
+
+// ============================================================================
+// 3 KM MODE PARAMETERS (both 50T and 200T)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_3KM   3000    // 30 us at 100 MSPS
+`define RP_LONG_SEGMENTS_3KM        2       // ceil((3000-2048)/1920) + 1 = 2
+`define RP_SHORT_CHIRP_SAMPLES      50      // 0.5 us at 100 MSPS (same both modes)
+`define RP_SHORT_SEGMENTS           1       // Single segment for short chirp
+
+// Derived 3 km limits
+`define RP_MAX_RANGE_3KM            3072    // 512 bins * 6 m = 3072 m
+
+// ============================================================================
+// 20 KM MODE PARAMETERS (200T only — Phase 2)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_20KM  13700   // 137 us at 100 MSPS (= listen window)
+`define RP_LONG_SEGMENTS_20KM       8       // 1 + ceil((13700-2048)/1920) = 1 + 7 = 8
+`define RP_OUTPUT_RANGE_BINS_20KM   4096    // 8 segments * 512 dec. bins each
+
+// Derived 20 km limits
+`define RP_MAX_RANGE_20KM           24576   // 4096 bins * 6 m = 24576 m
+
+// ============================================================================
+// MAX VALUES (for sizing buffers — compile-time, based on board variant)
+// ============================================================================
+
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_MAX_SEGMENTS           8
+  `define RP_MAX_OUTPUT_BINS        4096
+  `define RP_MAX_CHIRP_SAMPLES      13700
+`else
+  `define RP_MAX_SEGMENTS           2
+  `define RP_MAX_OUTPUT_BINS        512
+  `define RP_MAX_CHIRP_SAMPLES      3000
+`endif
+
+// ============================================================================
+// BIT WIDTHS (derived from MAX values)
+// ============================================================================
+
+// Segment index: ceil(log2(MAX_SEGMENTS))
+//   50T:  log2(2) = 1 bit  (use 2 for safety)
+//   200T: log2(8) = 3 bits
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_SEGMENT_IDX_WIDTH      3
+  `define RP_RANGE_BIN_WIDTH_MAX    12      // ceil(log2(4096))
+  `define RP_DOPPLER_MEM_ADDR_W     17      // ceil(log2(4096*32)) = 17
+  `define RP_CFAR_MAG_ADDR_W        17      // ceil(log2(4096*32)) = 17
+`else
+  `define RP_SEGMENT_IDX_WIDTH      2
+  `define RP_RANGE_BIN_WIDTH_MAX    9       // ceil(log2(512))
+  `define RP_DOPPLER_MEM_ADDR_W     14      // ceil(log2(512*32)) = 14
+  `define RP_CFAR_MAG_ADDR_W        14      // ceil(log2(512*32)) = 14
+`endif
+
+// Derived depths (for memory declarations)
+// Usage: reg [15:0] mem [0:`RP_DOPPLER_MEM_DEPTH-1];
+`define RP_DOPPLER_MEM_DEPTH    (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
+`define RP_CFAR_MAG_DEPTH       (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
+
+// ============================================================================
+// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
+// ============================================================================
+// Reset defaults for host-configurable timing registers.
+// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
+
+`define RP_DEF_LONG_CHIRP_CYCLES    3000    // 30 us
+`define RP_DEF_LONG_LISTEN_CYCLES   13700   // 137 us
+`define RP_DEF_GUARD_CYCLES         17540   // 175.4 us
+`define RP_DEF_SHORT_CHIRP_CYCLES   50      // 0.5 us
+`define RP_DEF_SHORT_LISTEN_CYCLES  17450   // 174.5 us
+`define RP_DEF_CHIRPS_PER_ELEV      32
+
+// ============================================================================
+// BLIND ZONE CONSTANTS (informational, for comments and GUI)
+// ============================================================================
+// Long chirp blind zone:  c * 30 us / 2 = 4500 m
+// Short chirp blind zone: c * 0.5 us / 2 = 75 m
+
+`define RP_LONG_BLIND_ZONE_M        4500
+`define RP_SHORT_BLIND_ZONE_M       75
+
+// ============================================================================
+// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
+// ============================================================================
+// Range per ADC sample:     1.5 m  (stored as 15 in units of 0.1 m)
+// Range per decimated bin:  6.0 m  (stored as 60 in units of 0.1 m)
+// Processing rate:         100 MSPS
+
+`define RP_RANGE_PER_SAMPLE_DM      15      // 1.5 m in decimeters
+`define RP_RANGE_PER_BIN_DM         60      // 6.0 m in decimeters
+`define RP_PROCESSING_RATE_MHZ      100
+
+// ============================================================================
+// AGC DEFAULTS
+// ============================================================================
+`define RP_DEF_AGC_TARGET           200
+`define RP_DEF_AGC_ATTACK           1
+`define RP_DEF_AGC_DECAY            1
+`define RP_DEF_AGC_HOLDOFF          4
+
+// ============================================================================
+// CFAR DEFAULTS
+// ============================================================================
+`define RP_DEF_CFAR_GUARD           2
+`define RP_DEF_CFAR_TRAIN           8
+`define RP_DEF_CFAR_ALPHA           8'h30   // 3.0 in Q4.4
+`define RP_DEF_CFAR_MODE            2'b00   // CA-CFAR
+
+// ============================================================================
+// DETECTION DEFAULTS
+// ============================================================================
+`define RP_DEF_DETECT_THRESHOLD     10000
+
+// ============================================================================
+// RADAR MODE ENCODING (host_radar_mode, opcode 0x01)
+// ============================================================================
+`define RP_MODE_STM32_PASSTHROUGH   2'b00
+`define RP_MODE_AUTO_3KM            2'b01
+`define RP_MODE_SINGLE_DEBUG        2'b10
+`define RP_MODE_RESERVED            2'b11
+
+// ============================================================================
+// RANGE MODE ENCODING (host_range_mode, opcode 0x20)
+// ============================================================================
+`define RP_RANGE_MODE_3KM           2'b00
+`define RP_RANGE_MODE_LONG          2'b01
+`define RP_RANGE_MODE_RSVD2         2'b10
+`define RP_RANGE_MODE_RSVD3         2'b11
+
+// ============================================================================
+// STREAM CONTROL (host_stream_control, opcode 0x04, 6-bit)
+// ============================================================================
+// Bits [2:0]: Stream enable mask
+//   Bit 0 = range profile stream
+//   Bit 1 = doppler map stream
+//   Bit 2 = cfar/detection stream
+// Bits [5:3]: Stream format control
+//   Bit 3 = mag_only    (0=I/Q pairs, 1=Manhattan magnitude only)
+//   Bit 4 = sparse_det  (0=dense detection flags, 1=sparse detection list)
+//   Bit 5 = reserved (was frame_decimate, not needed with mag-only fitting)
+`define RP_STREAM_CTRL_DEFAULT      6'b001_111  // all streams, mag-only mode
+
+`endif // RADAR_PARAMS_VH

9_Firmware/9_2_FPGA/range_bin_decimator.v

@@ -3,7 +3,7 @@
 /**
  * range_bin_decimator.v
  *
- * Reduces 1024 range bins from the matched filter output down to 64 bins
+ * Reduces 2048 range bins from the matched filter output down to 512 bins
  * for the Doppler processor. Supports multiple decimation modes:
  *
  *   Mode 2'b00: Simple decimation (take every Nth sample)
@@ -11,29 +11,31 @@
  *   Mode 2'b10: Averaging (sum group and divide by N)
  *   Mode 2'b11: Reserved
  *
- * Interface contract (from radar_receiver_final.v line 229):
+ * Interface contract (from radar_receiver_final.v):
  *   .clk, .reset_n
- *   .range_i_in, .range_q_in, .range_valid_in   ← from matched_filter output
- *   .range_i_out, .range_q_out, .range_valid_out → to Doppler processor
- *   .range_bin_index                             → 6-bit output bin index
- *   .decimation_mode                             ← 2-bit mode select
- *   .start_bin                                   ← 10-bit start offset
+ *   .range_i_in, .range_q_in, .range_valid_in   <- from matched_filter output
+ *   .range_i_out, .range_q_out, .range_valid_out -> to Doppler processor
+ *   .range_bin_index                             -> 9-bit output bin index
+ *   .decimation_mode                             <- 2-bit mode select
+ *   .start_bin                                   <- 11-bit start offset
  *
  * start_bin usage:
  *   When start_bin > 0, the decimator skips the first 'start_bin' valid
  *   input samples before beginning decimation. This allows selecting a
- *   region of interest within the 1024 range bins (e.g., to focus on
+ *   region of interest within the 2048 range bins (e.g., to focus on
  *   near-range or far-range targets). When start_bin = 0 (default),
- *   all 1024 bins are processed starting from bin 0.
+ *   all 2048 bins are processed starting from bin 0.
  *
  * Clock domain: clk (100 MHz)
- * Decimation: 1024 → 64 (factor of 16)
+ * Decimation: 2048 -> 512 (factor of 4)
  */
 
+`include "radar_params.vh"
+
 module range_bin_decimator #(
-    parameter INPUT_BINS        = 1024,
-    parameter OUTPUT_BINS       = 64,
-    parameter DECIMATION_FACTOR = 16
+    parameter INPUT_BINS        = `RP_FFT_SIZE,          // 2048
+    parameter OUTPUT_BINS       = `RP_NUM_RANGE_BINS,    // 512
+    parameter DECIMATION_FACTOR = `RP_DECIMATION_FACTOR  // 4
 ) (
     input wire clk,
     input wire reset_n,
@@ -47,11 +49,11 @@ module range_bin_decimator #(
     output reg signed [15:0] range_i_out,
     output reg signed [15:0] range_q_out,
     output reg range_valid_out,
-    output reg [5:0] range_bin_index,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_index,  // 9-bit
 
     // Configuration
     input wire [1:0] decimation_mode,  // 00=decimate, 01=peak, 10=average
-    input wire [9:0] start_bin,        // First input bin to process
+    input wire [10:0] start_bin,       // First input bin to process (11-bit for 2048)
 
     // Diagnostics
     output reg watchdog_timeout        // Pulses high for 1 cycle on watchdog reset
@@ -59,10 +61,10 @@ module range_bin_decimator #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [9:0]  fv_in_bin_count,
-    output wire [3:0]  fv_group_sample_count,
-    output wire [5:0]  fv_output_bin_count,
-    output wire [9:0]  fv_skip_count
+    output wire [10:0] fv_in_bin_count,
+    output wire [1:0]  fv_group_sample_count,
+    output wire [8:0]  fv_output_bin_count,
+    output wire [10:0] fv_skip_count
 `endif
 );
 
@@ -75,12 +77,12 @@ localparam WATCHDOG_LIMIT = 10'd256;
 // INTERNAL SIGNALS
 // ============================================================================
 
-// Input bin counter (0..1023)
-reg [9:0] in_bin_count;
+// Input bin counter (0..2047)
+reg [10:0] in_bin_count;
 
 // Group tracking
-reg [3:0] group_sample_count;  // 0..15 within current group of 16
-reg [5:0] output_bin_count;    // 0..63 output bin index
+reg [1:0] group_sample_count;   // 0..3 within current group of 4
+reg [8:0] output_bin_count;     // 0..511 output bin index
 
 // State machine
 reg [2:0] state;
@@ -91,7 +93,7 @@ localparam ST_EMIT    = 3'd3;
 localparam ST_DONE    = 3'd4;
 
 // Skip counter for start_bin
-reg [9:0] skip_count;
+reg [10:0] skip_count;
 
 // Watchdog counter — counts consecutive clocks with no range_valid_in
 reg [9:0] watchdog_count;
@@ -107,7 +109,7 @@ assign fv_skip_count         = skip_count;
 // ============================================================================
 // PEAK DETECTION (Mode 01)
 // ============================================================================
-// Track the sample with the largest magnitude in the current group of 16
+// Track the sample with the largest magnitude in the current group of 4
 reg signed [15:0] peak_i, peak_q;
 reg [16:0] peak_mag;  // |I| + |Q| approximation
 wire [16:0] cur_mag;
@@ -120,8 +122,8 @@ assign cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 // ============================================================================
 // AVERAGING (Mode 10)
 // ============================================================================
-// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>4)
-reg signed [19:0] sum_i, sum_q;  // 16 + 4 guard bits for sum of 16 values
+// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>2)
+reg signed [17:0] sum_i, sum_q;  // 16 + 2 guard bits for sum of 4 values
 
 // ============================================================================
 // SIMPLE DECIMATION (Mode 00)
@@ -135,21 +137,21 @@ reg signed [15:0] decim_i, decim_q;
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         state             <= ST_IDLE;
-        in_bin_count      <= 10'd0;
-        group_sample_count <= 4'd0;
-        output_bin_count  <= 6'd0;
-        skip_count        <= 10'd0;
+        in_bin_count      <= 11'd0;
+        group_sample_count <= 2'd0;
+        output_bin_count  <= 9'd0;
+        skip_count        <= 11'd0;
         watchdog_count    <= 10'd0;
         watchdog_timeout  <= 1'b0;
         range_valid_out   <= 1'b0;
         range_i_out       <= 16'd0;
         range_q_out       <= 16'd0;
-        range_bin_index   <= 6'd0;
+        range_bin_index   <= {`RP_RANGE_BIN_BITS{1'b0}};
         peak_i            <= 16'd0;
         peak_q            <= 16'd0;
         peak_mag          <= 17'd0;
-        sum_i             <= 20'd0;
-        sum_q             <= 20'd0;
+        sum_i             <= 18'd0;
+        sum_q             <= 18'd0;
         decim_i           <= 16'd0;
         decim_q           <= 16'd0;
     end else begin
@@ -162,33 +164,33 @@ always @(posedge clk or negedge reset_n) begin
         // IDLE: Wait for first valid input
         // ================================================================
         ST_IDLE: begin
-            in_bin_count       <= 10'd0;
-            group_sample_count <= 4'd0;
-            output_bin_count   <= 6'd0;
-            skip_count         <= 10'd0;
+            in_bin_count       <= 11'd0;
+            group_sample_count <= 2'd0;
+            output_bin_count   <= 9'd0;
+            skip_count         <= 11'd0;
             watchdog_count     <= 10'd0;
             peak_i             <= 16'd0;
             peak_q             <= 16'd0;
             peak_mag           <= 17'd0;
-            sum_i              <= 20'd0;
-            sum_q              <= 20'd0;
+            sum_i              <= 18'd0;
+            sum_q              <= 18'd0;
 
             if (range_valid_in) begin
-                in_bin_count <= 10'd1;
+                in_bin_count <= 11'd1;
 
-                if (start_bin > 10'd0) begin
+                if (start_bin > 11'd0) begin
                     // Need to skip 'start_bin' samples first
-                    skip_count <= 10'd1;
+                    skip_count <= 11'd1;
                     state      <= ST_SKIP;
                 end else begin
                     // No skip — process first sample immediately
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     // Mode-specific first sample handling
                     case (decimation_mode)
                     2'b00: begin  // Simple decimation — check if center sample
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -199,8 +201,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin  // Averaging
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -219,11 +221,11 @@ always @(posedge clk or negedge reset_n) begin
                 if (skip_count >= start_bin) begin
                     // Done skipping — this sample is the first to process
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -234,8 +236,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -281,8 +283,8 @@ always @(posedge clk or negedge reset_n) begin
                     end
                 end
                 2'b10: begin  // Averaging
-                    sum_i <= sum_i + {{4{range_i_in[15]}}, range_i_in};
-                    sum_q <= sum_q + {{4{range_q_in[15]}}, range_q_in};
+                    sum_i <= sum_i + {{2{range_i_in[15]}}, range_i_in};
+                    sum_q <= sum_q + {{2{range_q_in[15]}}, range_q_in};
                 end
                 default: ;
                 endcase
@@ -291,7 +293,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (group_sample_count == DECIMATION_FACTOR - 1) begin
                     // Group complete — emit output
                     state <= ST_EMIT;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end else if (in_bin_count >= INPUT_BINS - 1) begin
                     // Overflow guard: consumed all input bins but group
                     // is not yet complete. Stop to prevent corruption of
@@ -331,9 +333,9 @@ always @(posedge clk or negedge reset_n) begin
                 range_i_out <= peak_i;
                 range_q_out <= peak_q;
             end
-            2'b10: begin  // Averaging (sum >> 4 = divide by 16)
-                range_i_out <= sum_i[19:4];
-                range_q_out <= sum_q[19:4];
+            2'b10: begin  // Averaging (sum >> 2 = divide by 4)
+                range_i_out <= sum_i[17:2];
+                range_q_out <= sum_q[17:2];
             end
             default: begin
                 range_i_out <= 16'd0;
@@ -345,8 +347,8 @@ always @(posedge clk or negedge reset_n) begin
             peak_i   <= 16'd0;
             peak_q   <= 16'd0;
             peak_mag <= 17'd0;
-            sum_i    <= 20'd0;
-            sum_q    <= 20'd0;
+            sum_i    <= 18'd0;
+            sum_q    <= 18'd0;
 
             // Advance output bin
             output_bin_count <= output_bin_count + 1;
@@ -358,12 +360,12 @@ always @(posedge clk or negedge reset_n) begin
                 // If we already have valid input waiting, process it immediately
                 if (range_valid_in) begin
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
                     in_bin_count       <= in_bin_count + 1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -374,20 +376,20 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
                 end else begin
                     state <= ST_PROCESS;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end
             end
         end
 
         // ================================================================
-        // DONE: All 64 output bins emitted, return to idle
+        // DONE: All 512 output bins emitted, return to idle
         // ================================================================
         ST_DONE: begin
             state <= ST_IDLE;

9_Firmware/9_2_FPGA/rx_gain_control.v

@@ -54,7 +54,7 @@ module rx_gain_control (
     input  wire [3:0]  agc_decay,      // 0x2B: amplification step when weak (default 1)
     input  wire [3:0]  agc_holdoff,    // 0x2C: frames to wait before gain-up (default 4)
 
-    // Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
+    // Frame boundary pulse (1 clk cycle, from edge detector in radar_receiver_final)
     input  wire        frame_boundary,
 
     // Data output (to matched filter)

9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py

@@ -2,34 +2,22 @@
 """
 gen_chirp_mem.py — Generate all chirp .mem files for AERIS-10 FPGA.
 
-Generates the 10 chirp .mem files used by chirp_memory_loader_param.v:
-  - long_chirp_seg{0,1,2,3}_{i,q}.mem  (8 files, 1024 lines each)
-  - short_chirp_{i,q}.mem              (2 files, 50 lines each)
+Generates the 6 chirp .mem files used by chirp_memory_loader_param.v:
+  - long_chirp_seg{0,1}_{i,q}.mem  (4 files, 2048 lines each)
+  - short_chirp_{i,q}.mem          (2 files, 50 lines each)
 
 Long chirp:
   The 3000-sample baseband chirp (30 us at 100 MHz system clock) is
-  segmented into 4 blocks of 1024 samples.  Each segment covers a
+  segmented into 2 blocks of 2048 samples.  Each segment covers a
   different time window of the chirp:
-    seg0: samples   0 .. 1023
-    seg1: samples 1024 .. 2047
-    seg2: samples 2048 .. 3071  (only 952 valid chirp samples; 72 zeros)
-    seg3: all zeros (seg3 starts at sample 3072, past chirp end at 3000)
+    seg0: samples    0 .. 2047
+    seg1: samples 2048 .. 4095  (only 952 valid chirp samples; 1096 zeros)
 
-  Wait — actually the memory loader stores 4*1024 = 4096 contiguous
-  samples indexed by {segment_select[1:0], sample_addr[9:0]}.  The
-  long chirp has 3000 samples, so:
-    seg0: chirp[0..1023]
-    seg1: chirp[1024..2047]
-    seg2: chirp[2048..2999] + 24 zeros  (samples 2048..3071 but chirp
-          ends at 2999, so indices 3000..3071 relative to full chirp
-          => mem indices 952..1023 in seg2 file are zero)
-
-  Wait, let me re-count.  seg2 covers global indices 2048..3071.
-  The chirp has samples 0..2999 (3000 samples).  So seg2 has valid
-  data at global indices 2048..2999 = 952 valid samples (seg2 file
-  indices 0..951), then zeros at file indices 952..1023 (72 zeros).
-
-  seg3 covers global indices 3072..4095, all past chirp end => all zeros.
+  The memory loader stores 2*2048 = 4096 contiguous samples indexed
+  by {segment_select[0], sample_addr[10:0]}.  The long chirp has
+  3000 samples, so:
+    seg0: chirp[0..2047] — all valid data
+    seg1: chirp[2048..2999] + 1096 zeros (samples past chirp end)
 
 Short chirp:
   50 samples (0.5 us at 100 MHz), same chirp formula with
@@ -56,10 +44,10 @@ CHIRP_BW = 20e6           # 20 MHz sweep bandwidth
 FS_SYS = 100e6            # System clock (100 MHz, post-CIC)
 T_LONG_CHIRP = 30e-6      # 30 us long chirp duration
 T_SHORT_CHIRP = 0.5e-6    # 0.5 us short chirp duration
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 LONG_CHIRP_SAMPLES = int(T_LONG_CHIRP * FS_SYS)   # 3000
 SHORT_CHIRP_SAMPLES = int(T_SHORT_CHIRP * FS_SYS)  # 50
-LONG_SEGMENTS = 4
+LONG_SEGMENTS = 2
 SCALE = 0.9               # Q15 scaling factor (matches radar_scene.py)
 Q15_MAX = 32767
 
@@ -187,13 +175,14 @@ def main():
     # Check magnitude envelope
     max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
 
-    # Check seg3 zero padding
-    seg3_i_path = os.path.join(MEM_DIR, 'long_chirp_seg3_i.mem')
-    with open(seg3_i_path) as f:
-        seg3_lines = [line.strip() for line in f if line.strip()]
-    nonzero_seg3 = sum(1 for line in seg3_lines if line != '0000')
+    # Check seg1 zero padding (samples 3000-4095 should be zero)
+    seg1_i_path = os.path.join(MEM_DIR, 'long_chirp_seg1_i.mem')
+    with open(seg1_i_path) as f:
+        seg1_lines = [line.strip() for line in f if line.strip()]
+    # Indices 952..2047 in seg1 (global 3000..4095) should be zero
+    nonzero_tail = sum(1 for line in seg1_lines[952:] if line != '0000')
 
-    if nonzero_seg3 == 0:
+    if nonzero_tail == 0:
         pass
     else:
         pass