From e3bd885be9ffebc24a30d45bf8e7a5f4f3fc5989 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Tue, 5 May 2026 11:30:25 +0545
Subject: [PATCH] =?UTF-8?q?fix(mcu):=20PR-W=20F-6.3=20=E2=80=94=20clear=20?=
 =?UTF-8?q?opposite=20REG=5FMISC=5FENABLES=20bit=20in=20setADTR1107Mode?=
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Latent bit-mask hygiene gap. setADTR1107Mode(TX) was asserting BIAS_EN
(bit 5) without first clearing LNA_BIAS_OUT_EN (bit 4); the RX branch
mirrored the bug. On any TX→RX→TX (or symmetric) transition through
this register both PA and LNA bias outputs would end up enabled
simultaneously. Production today only ever calls one direction at boot
and the opposite at shutdown — never both during normal operation —
so the bug was unreachable, but a future per-chirp SPI mode switch
would trip it.

Now each branch resetBit's the opposite enable before asserting its
own. 1 line per branch loop (not 1 per device — used the existing
for-dev loop).
---
 .../9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp b/9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp
index 15124eb..c93a93a 100644
--- a/9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp
+++ b/9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp
@@ -373,10 +373,13 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
 
         // Step 5: TR switch state is FPGA-driven. TR_SOURCE=1 is set once in
         // initializeSingleDevice, so the chip already follows adar_tr_x.
-        // Only BIAS_EN needs to be asserted here.
-        DIAG("BF", "  BIAS_EN (TR source still = FPGA adar_tr_x)");
+        // Audit F-6.3: clear LNA_BIAS_OUT_EN before asserting BIAS_EN so a
+        // prior RX-armed state can't leave both PA and LNA bias outputs hot
+        // simultaneously through a TX→RX→TX (or RX→TX) transition.
+        DIAG("BF", "  clear LNA_BIAS_OUT_EN, set BIAS_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN
+            adarResetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN -> 0
+            adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF);   // BIAS_EN -> 1
         }
         DIAG("BF", "  ADTR1107 TX mode complete");
 
@@ -414,10 +417,13 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
         HAL_Delay(5);
 
         // Step 5: TR switch state is FPGA-driven (TR_SOURCE left at 1).
-        // Only LNA_BIAS_OUT_EN needs to be asserted here.
-        DIAG("BF", "  LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
+        // Audit F-6.3: clear BIAS_EN before asserting LNA_BIAS_OUT_EN to avoid
+        // both PA and LNA bias outputs being enabled at the same time on a
+        // TX→RX (or RX→TX→RX) transition.
+        DIAG("BF", "  clear BIAS_EN, set LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN
+            adarResetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN -> 0
+            adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF);   // LNA_BIAS_OUT_EN -> 1
         }
         DIAG("BF", "  ADTR1107 RX mode complete");
     }