From e97e55dd6330f7f761d659b4b27299d8facdb134 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Thu, 30 Apr 2026 09:04:01 +0545 Subject: [PATCH] AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `output_bin_count` is declared `reg [RP_RANGE_BIN_WIDTH_MAX-1:0]` (9 bits on 50T, 12 bits on 200T), but the reset and ST_IDLE assignments used the literal `9'd0`. Vivado zero-extends with a width-mismatch warning on 200T. The FORMAL port `fv_output_bin_count` was also hardcoded `[8:0]`. Replace all three sites with `{RP_RANGE_BIN_WIDTH_MAX{1'b0}}` / parameterized port width — same pattern already used for the `range_bin_index` reset in this module. No functional change. Verified by full FPGA regression: 41/41 PASS, 0 lint errors (Range Bin Decimator: 63 checks PASS). --- 9_Firmware/9_2_FPGA/range_bin_decimator.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/9_Firmware/9_2_FPGA/range_bin_decimator.v b/9_Firmware/9_2_FPGA/range_bin_decimator.v index b24add5..835b701 100644 --- a/9_Firmware/9_2_FPGA/range_bin_decimator.v +++ b/9_Firmware/9_2_FPGA/range_bin_decimator.v @@ -67,7 +67,7 @@ module range_bin_decimator #( output wire [2:0] fv_state, output wire [10:0] fv_in_bin_count, output wire [1:0] fv_group_sample_count, - output wire [8:0] fv_output_bin_count, + output wire [`RP_RANGE_BIN_WIDTH_MAX-1:0] fv_output_bin_count, output wire [10:0] fv_skip_count `endif ); @@ -143,7 +143,7 @@ always @(posedge clk or negedge reset_n) begin state <= ST_IDLE; in_bin_count <= 11'd0; group_sample_count <= 2'd0; - output_bin_count <= 9'd0; + output_bin_count <= {`RP_RANGE_BIN_WIDTH_MAX{1'b0}}; skip_count <= 11'd0; watchdog_count <= 10'd0; watchdog_timeout <= 1'b0; @@ -170,7 +170,7 @@ always @(posedge clk or negedge reset_n) begin ST_IDLE: begin in_bin_count <= 11'd0; group_sample_count <= 2'd0; - output_bin_count <= 9'd0; + output_bin_count <= {`RP_RANGE_BIN_WIDTH_MAX{1'b0}}; skip_count <= 11'd0; watchdog_count <= 10'd0; peak_i <= 16'd0;