3 Commits

Author	SHA1	Message	Date
Serhii	49055a8bf1	fix(ci): restore develop CI green — ruff T20 exemption + ADAR1000 setter regex extension ... Two independent root causes landed together in the recent develop merge burst, leaving CI red on every commit since. Both fixes are narrow parser/ config updates; no code logic changes. 1. Ruff T201 violation in 8_Utils/Python/LUT.py:24 The recent restoration of `print(f"8'd{val},")` (replacing `pass`) made the LUT generator functional again, but the file is not in pyproject's per-file-ignores so ruff's T20 rule flags it. Add a narrow per-file- ignore for T20 specifically scoped to LUT.py. 2. Five tests in TestTier1Adar1000ChannelRegisterRoundTrip The recent SPI/ADC error-propagation refactor on ADAR1000_Manager.cpp changed the four setters adarSet{Rx,Tx}{Phase,VgaGain} from `void` to `bool` returns AND introduced the `ok = setter(args) && ok` error-chain idiom at internal call sites. The test class's parser regexes were authored for the pre-refactor convention. Two regex extensions: * Body parser: `void\s+...` -> `(?:void|bool)\s+...` so bodies are found under either return-type convention. * Caller finder: `\)\s*;` -> `\)(?:\s*&&\s*\w+)*\s*;` so the error-chain idiom is matched alongside standalone calls. Body extraction logic, REG_CHn_XXX + <expr> regex, symbolic AST evaluation, round-trip strict-equality, and stride detection are all unchanged. The two regex extensions only acknowledge the new C++ conventions introduced by the SPI/ADC refactor. Verified locally: - `uv run ruff check .` returns 0 errors. - `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py` passes 51 tests + 5 skipped (Tier2VerilogCosim local-only, requires iverilog which is installed in CI). - `uv run pytest 9_Firmware/9_3_GUI/test_v7.py` passes 83 tests + 3 skipped (no regression).	2026-05-07 07:50:34 +03:00
Jason	2106e24952	fix: enforce strict ruff lint (17 rule sets) across entire repo ... - Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20, ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF) - Fix 907 lint errors across all Python files (GUI, FPGA cosim, schematics scripts, simulations, utilities, tools) - Replace all blind except-Exception with specific exception types - Remove commented-out dead code (ERA001) from cosim/simulation files - Modernize typing: deprecated typing.List/Dict/Tuple to builtins - Fix unused args/loop vars, ambiguous unicode, perf anti-patterns - Delete legacy GUI files V1-V4 - Add V7 test suite, requirements files - All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92), MCU tests (20/20), FPGA regression (25/25)	2026-04-12 14:21:03 +05:45
Jason	11aa590cf2	fix: full-repo ruff lint cleanup and CI migration to uv ... Resolve all 374 ruff errors across 36 Python files (E501, E702, E722, E741, F821, F841, invalid-syntax) bringing `ruff check .` to zero errors repo-wide with line-length=100. Rewrite CI workflow to use uv for dependency management, whole-repo `ruff check .`, py_compile syntax gate, and merged python-tests job. Add pyproject.toml with ruff config and uv dependency groups. CI structure proposed by hcm444.	2026-04-09 02:05:34 +03:00