Jason ca2b6e527d fix(fpga): TX-G — surface chirps_mismatch_error to host status ...

`chirps_mismatch_error` was set in radar_system_top when the host
requested chirps_per_elev != Doppler FFT size, but never wired into the
USB status response — a latent silent failure.

Wired the flag through both USB interfaces (FT601 + FT2232H) into bit
[10] of status word 4 (was reserved). GUI parser exposes it as
StatusResponse.chirps_mismatch.

- usb_data_interface*.v: new status_chirps_mismatch input, packed at [10]
- radar_system_top.v: connect chirps_mismatch_error to both USB instances
- radar_protocol.py + test_GUI_V65_Tk.py: parse new bit, +1 round-trip test
- tb_usb_data_interface.v: drive the new port, update word-4 expectation

Tests: GUI 92/92 (was 91), MCU 75/75, USB TB 91/91, ruff clean repo-wide.
The 2 remaining FPGA regression failures (Receiver Integration, MF Chain)
are the pre-existing iverilog-can't-link-Xilinx-IP issue tracked
separately as the open RX-NEW-3 follow-up.

2026-04-24 11:06:26 +05:45

..

9_1_Microcontroller

fix: MCU-N4 delay_us bound; GUI-S4 STREAM_CONTROL comment

2026-04-23 07:43:53 +05:45

9_2_FPGA

fix(fpga): TX-G — surface chirps_mismatch_error to host status

2026-04-24 11:06:26 +05:45

9_3_GUI

fix(fpga): TX-G — surface chirps_mismatch_error to host status

2026-04-24 11:06:26 +05:45

tests/cross_layer

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tools

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45