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6f68f3263a
MCU-N4: delay_us(us) reset TIM1 then waited for the counter to reach `us`, but TIM1 ARR is 0xffff-1 (~65 ms at the 1 MHz tick). Any caller passing us > 65534 spun forever after the first wrap — a real hazard with the PA energized. Chunk requests larger than ARR into ARR-sized waits, then the remainder in the existing single wait. Current callers (T1, PRI1-T1, Guard, 500us spots) are all well under the bound; this is defensive. GUI-S4: radar_protocol.STREAM_CONTROL was annotated "3-bit stream enable mask"; the FPGA accepts usb_cmd_value[5:0] = 6 bits. The wire protocol already carried the full 32-bit value field, so the upper bits were reachable via Custom Command — only the comment was wrong. Updated to match radar_system_top.v:1004. Verified: 75/75 MCU tests pass; 83/83 v7 GUI tests pass (covered by GUI-C3 commit).