Jason e3bd885be9 fix(mcu): PR-W F-6.3 — clear opposite REG_MISC_ENABLES bit in setADTR1107Mode ...

Latent bit-mask hygiene gap. setADTR1107Mode(TX) was asserting BIAS_EN
(bit 5) without first clearing LNA_BIAS_OUT_EN (bit 4); the RX branch
mirrored the bug. On any TX→RX→TX (or symmetric) transition through
this register both PA and LNA bias outputs would end up enabled
simultaneously. Production today only ever calls one direction at boot
and the opposite at shutdown — never both during normal operation —
so the bug was unreachable, but a future per-chirp SPI mode switch
would trip it.

Now each branch resetBit's the opposite enable before asserting its
own. 1 line per branch loop (not 1 per device — used the existing
for-dev loop).

2026-05-05 11:30:25 +05:45

..

9_1_Microcontroller

fix(mcu): PR-W F-6.3 — clear opposite REG_MISC_ENABLES bit in setADTR1107Mode

2026-05-05 11:30:25 +05:45

9_2_FPGA

chore(repo): PR-H — G-series close-out (regression infra + lint sweep)

2026-05-05 10:39:57 +05:45

9_3_GUI

test(v7): port live-vs-replay physical-units parity guard from develop

2026-05-05 09:30:26 +05:45

tests/cross_layer

chore(tests): retire v1 cross-layer iverilog cosim tier

2026-05-04 21:06:34 +05:45

tools

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45