cosim: refresh stale baselines (FFT-2048 + chirp realign)

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Two stale-baseline events were never captured in earlier commits:

1. The FFT-1024 -> FFT-2048 merge (c668652) updated the testbench and
   gen_mf_cosim_golden.py but left radar_scene.py FFT_SIZE=1024. When
   FFT_SIZE was later bumped to 2048, the input vectors written by
   generate_baseband_samples (bb_mf_test_*.hex, ref_chirp_*.hex) grew
   from 1024 to 2048 samples but were never re-exported.

2. The TX-I matched-filter realignment (5ff5671) changed the ADC chirp
   phase from 2*pi*F_IF*t to 2*pi*(F_IF+F_BASEBAND_LOW)*t. ADC sample
   values shifted from sample ~1336 onward but adc_*.hex was never
   re-exported.

Result: every regression run produced a "dirty" working tree as the
regen reproduced post-merge values that disagreed with the committed
baselines. Two consecutive regen runs are bit-exact identical
(LCG seed=42 + deterministic chirp math) — verified via diff -q on
two output dirs. There is no actual non-determinism; only stale
artifacts.

This commit refreshes all 15 affected files in one shot:
- 6 input hex (adc_*_target.hex, bb_mf_test_*.hex, ref_chirp_*.hex)
- 5 RTL output csv (rtl_*.csv from current RTL)
- 4 compare csv (compare_mf_*.csv = py vs rtl side-by-side)

Verification: full regression 39/39 PASS on the refreshed inputs.
After this commit, regression runs should leave the working tree clean.

...

This commit is contained in:

Jason

2026-04-29 20:33:55 +05:45

parent 58154a6bf1

commit 1f307f77a9

15 changed files with 44870 additions and 40774 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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9_Firmware/9_2_FPGA/tb/cosim/adc_multi_target.hex

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9_Firmware/9_2_FPGA/tb/cosim/adc_single_target.hex

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9_Firmware/9_2_FPGA/tb/cosim/bb_mf_test_i.hex

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9_Firmware/9_2_FPGA/tb/cosim/bb_mf_test_q.hex

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9_Firmware/9_2_FPGA/tb/cosim/compare_mf_chirp.csv

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9_Firmware/9_2_FPGA/tb/cosim/compare_mf_dc.csv

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1024

9_Firmware/9_2_FPGA/tb/cosim/compare_mf_impulse.csv

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9_Firmware/9_2_FPGA/tb/cosim/compare_mf_tone5.csv

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9_Firmware/9_2_FPGA/tb/cosim/ref_chirp_i.hex

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9_Firmware/9_2_FPGA/tb/cosim/ref_chirp_q.hex

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9_Firmware/9_2_FPGA/tb/cosim/rtl_bb_dc.csv

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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_chirp.csv

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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_dc.csv

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1024

9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_impulse.csv

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4096

9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_tone5.csv

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