mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
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fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)
matched_filter_multi_segment.v ingestion model rewritten to capture the
full chirp into a single 4096-deep input BRAM during ST_COLLECT_DATA,
then slide non-destructive segment windows over the stable buffer:
segment N reads buffer[N*SEGMENT_ADVANCE .. N*SEGMENT_ADVANCE+2047]
segment_offset advances by SEGMENT_ADVANCE in ST_NEXT_SEGMENT.
Replaces the original overlap-save scheme, which assumed the input ddc
stream stayed live across segment processing. That contract breaks
because chain processing (~70 us at production xfft_2048 timing,
~1.7 ms in the iverilog batched fallback) outlasts the LONG chirp
duration (30 us). Segment-1 input samples (chirp samples 2048..2999)
arrived during segment 0's ST_PROCESSING / ST_WAIT_FFT and were
silently dropped, so segment 1 hung forever in ST_COLLECT_DATA waiting
for ddc_valid that never came. PR-J.1 (8b6f2ec) localised the failure;
this is the fix.
Removed:
ST_OVERLAP_COPY state (state 8)
overlap_cache_i/q (128-entry distributed RAM)
overlap_copy_count, ov_we / ov_waddr / ov_wdata signals
overlap_cache write port + accompanying always block
ST_PROCESSING's mid-stream tail-cache writes
Added:
segment_offset (12-bit, advances by SEGMENT_ADVANCE per segment)
samples_fed (12-bit per-segment FFT-input counter)
LONG_FILL_END parameter ((LONG_SEGMENTS-1)*SEGMENT_ADVANCE +
BUFFER_SIZE = 3968 for 50T)
Address-width changes:
buffer_write_ptr / buffer_read_ptr / buf_waddr / buf_raddr 11-bit
-> 12-bit (INPUT_BUF_ADDR_W)
sample_addr_out (port to chirp_reference_rom) now driven from
samples_fed[10:0] — per-segment 0..2047 contract preserved.
State machine summary:
ST_IDLE -> ST_COLLECT_DATA on chirp_pulse
ST_COLLECT_DATA -> ST_ZERO_PAD when full chirp ingested
ST_ZERO_PAD -> ST_WAIT_REF (segment 0)
ST_WAIT_REF -> ST_PROCESSING (mem_ready, buf_raddr presented at
segment_offset)
ST_PROCESSING -> ST_WAIT_FFT after FFT_SIZE samples fed
ST_WAIT_FFT -> ST_OUTPUT on chain idle + saw_chain_output
ST_OUTPUT -> ST_NEXT_SEGMENT (more segments) | ST_IDLE (done)
ST_NEXT_SEGMENT -> ST_WAIT_REF (segment_offset += SEGMENT_ADVANCE,
segment_request bumped, mem_request)
Verification (tb_mf_long_chirp, +WAVE=N):
SHORT (1 segment): 2048/2048 pc_valid pulses, 167997 cycles
MEDIUM (1 segment): 2048/2048 pc_valid pulses, 167997 cycles
LONG (2 segments): 4096/4096 pc_valid pulses, 335858 cycles
-- vs pre-PR-J.2 LONG: hung in ST_COLLECT_DATA, 2048/4096.
Full regression: 41 passed / 1 failed (only failure is the pre-existing
FFT Engine test, unrelated to this PR — same baseline as pre-PR-J.2).
200T (SUPPORT_LONG_RANGE) variant will need INPUT_BUF_DEPTH bumped to
16384; a runtime parameter or `ifdef can wire that when 200T is
actually built. tb_mf_long_chirp HARD_BUDGET_CYCLES bumped 200k -> 500k
to fit two iverilog-fallback FFT passes.
This commit is contained in:
Jason
@@ -41,7 +41,7 @@ module matched_filter_multi_segment (
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);
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// ========== FIXED PARAMETERS ==========
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parameter BUFFER_SIZE = `RP_FFT_SIZE; // 2048
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parameter BUFFER_SIZE = `RP_FFT_SIZE; // 2048 (FFT pass size)
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parameter LONG_CHIRP_SAMPLES = 3000; // 30 us @ 100 MHz
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parameter MEDIUM_CHIRP_SAMPLES = 500; // 5 us @ 100 MHz (chirp-v2)
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parameter SHORT_CHIRP_SAMPLES = 100; // 1 us @ 100 MHz (chirp-v2; was 50)
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@@ -49,11 +49,35 @@ parameter OVERLAP_SAMPLES = `RP_OVERLAP_SAMPLES; // 128
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parameter SEGMENT_ADVANCE = `RP_SEGMENT_ADVANCE; // 2048 - 128 = 1920 samples
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parameter DEBUG = 1; // Debug output control
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// Segment counts (overlap-save). LONG spans 2 segments; SHORT and MEDIUM
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// both fit in a single 2048 buffer with zero-pad.
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parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM; // 2 segments (30 us / 2048-128 overlap)
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// Segment counts. LONG spans 2 segments; SHORT and MEDIUM both fit in a
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// single 2048-sample window with zero-pad.
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parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM; // 2 segments (30 us)
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parameter SHORT_SEGMENTS = 1; // SHORT or MEDIUM, single segment
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// PR-J.2: pre-collect-then-slide ingestion. The full chirp is captured into
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// INPUT_BUF_DEPTH-deep BRAM during ST_COLLECT_DATA, then segments are read
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// out non-destructively as 2048-sample windows starting at
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// current_segment * SEGMENT_ADVANCE. This replaces the original overlap-save
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// mechanism, which assumed the input ddc stream stayed live across segment
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// processing — a contract that breaks because chain processing (~70 us at
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// production xfft_2048 timing) outlasts the LONG chirp duration (30 us),
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// dropping segment-N>0 input samples.
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//
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// Required depth: (LONG_SEGMENTS - 1) * SEGMENT_ADVANCE + BUFFER_SIZE
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// 50T -> 1*1920 + 2048 = 3968 (round up to 4096)
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// 200T -> 7*1920 + 2048 = 15488 (would need 16384)
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// 50T-only here; 200T variant must bump INPUT_BUF_DEPTH when LONG_SEGMENTS
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// changes via SUPPORT_LONG_RANGE.
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parameter INPUT_BUF_DEPTH = 4096;
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parameter INPUT_BUF_ADDR_W = 12;
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// Total samples needed in buffer to cover LONG_SEGMENTS segments with
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// overlap-save indexing. Last segment ends at (LONG_SEGMENTS-1)*ADVANCE +
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// BUFFER_SIZE = 3968 (50T). ST_ZERO_PAD pads up to this point for LONG
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// chirps so segment 1's read window is well-defined even when the chirp
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// only delivers 3000 real samples.
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parameter LONG_FILL_END = (LONG_SEGMENTS - 1) * SEGMENT_ADVANCE + BUFFER_SIZE;
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// Convenience nets so the FSM body reads cleanly.
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wire is_long = (wave_sel == `RP_WAVE_LONG);
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wire is_medium = (wave_sel == `RP_WAVE_MEDIUM);
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@@ -62,23 +86,30 @@ wire is_medium = (wave_sel == `RP_WAVE_MEDIUM);
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reg signed [31:0] pc_i, pc_q;
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reg pc_valid;
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// Dual buffer for overlap-save — BRAM inferred for synthesis
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(* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:BUFFER_SIZE-1];
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(* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:BUFFER_SIZE-1];
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reg [11:0] buffer_write_ptr; // 12-bit for 0..2048
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reg [11:0] buffer_read_ptr; // 12-bit for 0..2048
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// Pre-collect input buffer (PR-J.2). Sized to hold the full LONG chirp plus
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// segment-1's read tail; SHORT/MEDIUM only use the first 2048 entries.
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(* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:INPUT_BUF_DEPTH-1];
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(* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:INPUT_BUF_DEPTH-1];
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reg [INPUT_BUF_ADDR_W-1:0] buffer_write_ptr;
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reg [INPUT_BUF_ADDR_W-1:0] buffer_read_ptr; // global address into input_buffer
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reg buffer_has_data;
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reg buffer_processing;
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reg [15:0] chirp_samples_collected;
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// Per-segment offset and feed counter — segment N reads buffer[segment_offset
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// .. segment_offset + FFT_SIZE - 1], where segment_offset advances by
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// SEGMENT_ADVANCE each ST_NEXT_SEGMENT.
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reg [INPUT_BUF_ADDR_W-1:0] segment_offset;
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reg [11:0] samples_fed; // 0..BUFFER_SIZE within a segment
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// BRAM write port signals
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reg buf_we;
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reg [10:0] buf_waddr; // 11-bit for 0..2047
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reg signed [15:0] buf_wdata_i, buf_wdata_q;
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reg buf_we;
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reg [INPUT_BUF_ADDR_W-1:0] buf_waddr;
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reg signed [15:0] buf_wdata_i, buf_wdata_q;
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// BRAM read port signals
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reg [10:0] buf_raddr; // 11-bit for 0..2047
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reg signed [15:0] buf_rdata_i, buf_rdata_q;
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reg [INPUT_BUF_ADDR_W-1:0] buf_raddr;
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reg signed [15:0] buf_rdata_i, buf_rdata_q;
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// State machine
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reg [3:0] state;
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@@ -90,7 +121,8 @@ localparam ST_PROCESSING = 4;
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localparam ST_WAIT_FFT = 5;
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localparam ST_OUTPUT = 6;
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localparam ST_NEXT_SEGMENT = 7;
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localparam ST_OVERLAP_COPY = 8;
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// State 8 (ST_OVERLAP_COPY) retired in PR-J.2 — pre-collected buffer is
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// stable across segments, so no overlap copy is needed.
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// Segment tracking
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reg [2:0] current_segment; // 0-3
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@@ -99,18 +131,6 @@ reg segment_done;
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reg chirp_complete;
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reg saw_chain_output; // Flag: chain started producing output
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// Overlap cache — captured during ST_PROCESSING, written back in ST_OVERLAP_COPY
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// Uses sync-only write block to allow distributed RAM inference (not FFs).
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// 128 entries = distributed RAM (LUTRAM), NOT BRAM (too shallow).
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reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
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reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
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reg [7:0] overlap_copy_count;
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// Overlap cache write port signals (driven from FSM, used in sync-only block)
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reg ov_we;
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reg [6:0] ov_waddr;
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reg signed [15:0] ov_wdata_i, ov_wdata_q;
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// Processing chain signals
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wire [15:0] fft_pc_i, fft_pc_q;
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wire fft_pc_valid;
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@@ -122,20 +142,18 @@ reg fft_input_valid;
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reg fft_start;
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// ========== SAMPLE ADDRESS OUTPUT ==========
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assign sample_addr_out = buffer_read_ptr[10:0];
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// chirp_reference_rom expects a per-segment 0..2047 address (the reference
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// window is segment-scoped, FFT_SIZE-deep). samples_fed counts FFT-input
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// position within the current segment, which is exactly that.
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assign sample_addr_out = samples_fed[10:0];
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// ========== BUFFER INITIALIZATION ==========
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integer buf_init;
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integer ov_init;
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initial begin
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for (buf_init = 0; buf_init < BUFFER_SIZE; buf_init = buf_init + 1) begin
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for (buf_init = 0; buf_init < INPUT_BUF_DEPTH; buf_init = buf_init + 1) begin
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input_buffer_i[buf_init] = 16'd0;
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input_buffer_q[buf_init] = 16'd0;
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end
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for (ov_init = 0; ov_init < OVERLAP_SAMPLES; ov_init = ov_init + 1) begin
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overlap_cache_i[ov_init] = 16'd0;
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overlap_cache_q[ov_init] = 16'd0;
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end
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end
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// ========== BRAM WRITE PORT (synchronous, no async reset) ==========
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@@ -146,16 +164,6 @@ always @(posedge clk) begin
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end
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end
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// ========== OVERLAP CACHE WRITE PORT (sync only — distributed RAM inference) ==========
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// Removing async reset from memory write path prevents Vivado from
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// synthesizing the 128x16 arrays as FFs + mux trees.
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always @(posedge clk) begin
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if (ov_we) begin
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overlap_cache_i[ov_waddr] <= ov_wdata_i;
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overlap_cache_q[ov_waddr] <= ov_wdata_q;
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end
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end
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// ========== BRAM READ PORT (synchronous, no async reset) ==========
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always @(posedge clk) begin
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buf_rdata_i <= input_buffer_i[buf_raddr];
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@@ -174,6 +182,8 @@ always @(posedge clk or negedge reset_n) begin
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current_segment <= 0;
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segment_done <= 0;
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segment_request <= 0;
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segment_offset <= 0;
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samples_fed <= 0;
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mem_request <= 0;
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pc_valid <= 0;
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status <= 0;
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@@ -187,17 +197,11 @@ always @(posedge clk or negedge reset_n) begin
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buf_wdata_i <= 0;
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buf_wdata_q <= 0;
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buf_raddr <= 0;
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ov_we <= 0;
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ov_waddr <= 0;
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ov_wdata_i <= 0;
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ov_wdata_q <= 0;
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overlap_copy_count <= 0;
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end else begin
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pc_valid <= 0;
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mem_request <= 0;
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fft_input_valid <= 0;
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buf_we <= 0; // Default: no write
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ov_we <= 0; // Default: no overlap write
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case (state)
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ST_IDLE: begin
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@@ -207,11 +211,13 @@ always @(posedge clk or negedge reset_n) begin
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buffer_has_data <= 0;
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buffer_processing <= 0;
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current_segment <= 0;
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segment_offset <= 0;
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samples_fed <= 0;
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segment_done <= 0;
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chirp_samples_collected <= 0;
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chirp_complete <= 0;
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saw_chain_output <= 0;
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// Wait for chirp start (1-cycle pulse from chirp_scheduler)
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if (chirp_pulse) begin
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state <= ST_COLLECT_DATA;
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@@ -228,176 +234,139 @@ always @(posedge clk or negedge reset_n) begin
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end
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ST_COLLECT_DATA: begin
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// Collect samples for current segment with overlap-save
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if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
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// Store in buffer via BRAM write port
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// PR-J.2: pre-collect entire chirp into the input buffer.
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// No mid-stream segment processing; segments slide over the
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// stable buffer once collection + zero-pad complete.
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if (ddc_valid && buffer_write_ptr < INPUT_BUF_DEPTH) begin
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buf_we <= 1;
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buf_waddr <= buffer_write_ptr[10:0];
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// [RX-A FIX] ddc_i = {{2{gc_i[15]}}, gc_i} — top 2 bits are
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// sign-extension. The previous `ddc_i[17:2] + ddc_i[1]`
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// was a gratuitous /4 scaling (~12 dB dynamic-range loss).
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// fft_engine has INTERNAL_W=32 with saturating 16-bit output,
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// so full 16-bit input is safe (no bit-growth overflow risk).
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buf_waddr <= buffer_write_ptr;
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// [RX-A FIX] ddc_i = {{2{gc_i[15]}}, gc_i} — top 2 bits
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// are sign-extension; full 16-bit input is safe because
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// fft_engine has INTERNAL_W=32 with saturating 16-bit
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// output (no bit-growth overflow risk).
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buf_wdata_i <= ddc_i[15:0];
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buf_wdata_q <= ddc_q[15:0];
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buffer_write_ptr <= buffer_write_ptr + 1;
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chirp_samples_collected <= chirp_samples_collected + 1;
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// Debug: Show first few samples
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if (chirp_samples_collected < 10 && buffer_write_ptr < 10) begin
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if (chirp_samples_collected < 10) begin
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] Store[%0d]: I=%h Q=%h",
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buffer_write_ptr,
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ddc_i[17:2] + ddc_i[1],
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ddc_q[17:2] + ddc_q[1]);
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$display("[MULTI_SEG_FIXED] Store[%0d]: I=%h Q=%h",
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buffer_write_ptr, ddc_i[15:0], ddc_q[15:0]);
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`endif
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end
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// SHORT/MEDIUM single-segment path: collect waveform-specific
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// sample count then zero-pad to 2048. SHORT=100 (1 us),
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// MEDIUM=500 (5 us). LONG path falls through to the
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// multi-segment overlap-save block below.
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if (!is_long) begin
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if (( is_medium && chirp_samples_collected >= MEDIUM_CHIRP_SAMPLES - 1) ||
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(!is_medium && chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1)) begin
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state <= ST_ZERO_PAD;
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chirp_complete <= 1; // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] %s chirp: collected %d samples, starting zero-pad",
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is_medium ? "Medium" : "Short",
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chirp_samples_collected + 1);
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`endif
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end
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end
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end
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// LONG CHIRP: segment-ready and chirp-complete checks
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// evaluated every clock (not gated by ddc_valid) to avoid
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// missing the transition when buffer_write_ptr updates via
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// non-blocking assignment one cycle after the last write.
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//
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// Overlap-save fix: fill the FULL FFT_SIZE-sample buffer before
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// processing. For segment 0 this means FFT_SIZE fresh samples.
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// For segments 1+, write_ptr starts at OVERLAP_SAMPLES (128)
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// so we collect 896 new samples to fill the buffer.
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if (is_long) begin
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if (buffer_write_ptr >= BUFFER_SIZE) begin
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buffer_has_data <= 1;
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state <= ST_WAIT_REF;
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segment_request <= current_segment[1:0];
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mem_request <= 1;
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] Segment %d ready: %d samples collected",
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current_segment, chirp_samples_collected);
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`endif
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end
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if (chirp_samples_collected >= LONG_CHIRP_SAMPLES && !chirp_complete) begin
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// Chirp-complete check (each-clock, not gated on ddc_valid,
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// so the transition fires the cycle after the last write).
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if (!chirp_complete) begin
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if (is_long &&
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chirp_samples_collected >= LONG_CHIRP_SAMPLES) begin
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chirp_complete <= 1;
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state <= ST_ZERO_PAD;
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] End of long chirp reached");
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$display("[MULTI_SEG_FIXED] LONG chirp: collected %0d samples, padding to %0d",
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chirp_samples_collected, LONG_FILL_END);
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`endif
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end else if (is_medium &&
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chirp_samples_collected >= MEDIUM_CHIRP_SAMPLES) begin
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chirp_complete <= 1;
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state <= ST_ZERO_PAD;
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] MEDIUM chirp: collected %0d samples, padding to %0d",
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chirp_samples_collected, BUFFER_SIZE);
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`endif
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end else if (!is_long && !is_medium &&
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chirp_samples_collected >= SHORT_CHIRP_SAMPLES) begin
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chirp_complete <= 1;
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state <= ST_ZERO_PAD;
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] SHORT chirp: collected %0d samples, padding to %0d",
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chirp_samples_collected, BUFFER_SIZE);
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`endif
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// If buffer isn't full yet, zero-pad the remainder
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// (last segment with fewer than 896 new samples)
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if (buffer_write_ptr < BUFFER_SIZE) begin
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state <= ST_ZERO_PAD;
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`ifdef SIMULATION
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$display("[MULTI_SEG_FIXED] Last segment partial: zero-padding from %0d to %0d",
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buffer_write_ptr, BUFFER_SIZE - 1);
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`endif
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end
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end
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end
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end
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ST_ZERO_PAD: begin
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// Zero-pad remaining buffer via BRAM write port
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// Zero-pad remaining buffer via BRAM write port. LONG pads
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// to LONG_FILL_END (covers all segments' read windows).
|
||||
// SHORT/MEDIUM pads to BUFFER_SIZE (single-segment).
|
||||
buf_we <= 1;
|
||||
buf_waddr <= buffer_write_ptr[10:0];
|
||||
buf_waddr <= buffer_write_ptr;
|
||||
buf_wdata_i <= 16'd0;
|
||||
buf_wdata_q <= 16'd0;
|
||||
buffer_write_ptr <= buffer_write_ptr + 1;
|
||||
|
||||
if (buffer_write_ptr >= BUFFER_SIZE - 1) begin
|
||||
// Done zero-padding
|
||||
|
||||
if ((is_long && buffer_write_ptr >= LONG_FILL_END - 1) ||
|
||||
(!is_long && buffer_write_ptr >= BUFFER_SIZE - 1)) begin
|
||||
buffer_has_data <= 1;
|
||||
buffer_write_ptr <= 0;
|
||||
state <= ST_WAIT_REF;
|
||||
segment_request <= is_long ? current_segment[1:0] : 2'd0;
|
||||
segment_request <= 2'd0;
|
||||
mem_request <= 1;
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Zero-pad complete, buffer full");
|
||||
$display("[MULTI_SEG_FIXED] Zero-pad complete, requesting segment 0 reference");
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
ST_WAIT_REF: begin
|
||||
// Wait for memory to provide reference coefficients
|
||||
buf_raddr <= 11'd0; // Pre-present addr 0 so buf_rdata is ready next cycle
|
||||
// Pre-present this segment's first read address so buf_rdata
|
||||
// holds buffer[segment_offset] on the first ST_PROCESSING clk.
|
||||
buf_raddr <= segment_offset;
|
||||
if (mem_ready) begin
|
||||
// Start processing — buf_rdata[0] will be valid on FIRST clock of ST_PROCESSING
|
||||
buffer_processing <= 1;
|
||||
buffer_read_ptr <= 0;
|
||||
fft_start <= 1;
|
||||
state <= ST_PROCESSING;
|
||||
|
||||
buffer_read_ptr <= segment_offset;
|
||||
samples_fed <= 0;
|
||||
fft_start <= 1;
|
||||
state <= ST_PROCESSING;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Reference ready, starting processing segment %d",
|
||||
current_segment);
|
||||
$display("[MULTI_SEG_FIXED] Reference ready, starting processing segment %0d (offset=%0d)",
|
||||
current_segment, segment_offset);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
ST_PROCESSING: begin
|
||||
// Feed data to FFT chain from BRAM.
|
||||
// buf_raddr was pre-presented in ST_WAIT_REF (=0), so
|
||||
// buf_rdata already contains data[0] on the first clock here.
|
||||
// Each cycle: feed buf_rdata, present NEXT address.
|
||||
if ((buffer_processing) && (buffer_read_ptr < BUFFER_SIZE)) begin
|
||||
// 1. Feed BRAM read data to FFT (valid for current buffer_read_ptr)
|
||||
fft_input_i <= buf_rdata_i;
|
||||
fft_input_q <= buf_rdata_q;
|
||||
fft_input_valid <= 1;
|
||||
|
||||
// 2. Request corresponding reference sample
|
||||
// Feed BUFFER_SIZE (FFT_SIZE) samples from buffer[segment_offset
|
||||
// .. segment_offset+FFT_SIZE-1] into the chain. samples_fed
|
||||
// counts within the segment; buffer_read_ptr is the global
|
||||
// BRAM address (= segment_offset + samples_fed).
|
||||
if (buffer_processing && samples_fed < BUFFER_SIZE) begin
|
||||
fft_input_i <= buf_rdata_i;
|
||||
fft_input_q <= buf_rdata_q;
|
||||
fft_input_valid <= 1;
|
||||
|
||||
// Request corresponding reference sample (per-segment
|
||||
// address; sample_addr_out is samples_fed[10:0]).
|
||||
mem_request <= 1'b1;
|
||||
|
||||
// 3. Cache tail samples for overlap-save (via sync-only write port)
|
||||
if (buffer_read_ptr >= SEGMENT_ADVANCE) begin
|
||||
ov_we <= 1;
|
||||
ov_waddr <= buffer_read_ptr - SEGMENT_ADVANCE; // 0..OVERLAP-1
|
||||
ov_wdata_i <= buf_rdata_i;
|
||||
ov_wdata_q <= buf_rdata_q;
|
||||
end
|
||||
|
||||
// Debug every 100 samples
|
||||
if (buffer_read_ptr % 100 == 0) begin
|
||||
|
||||
if (samples_fed % 100 == 0) begin
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Processing[%0d]: ADC I=%h Q=%h",
|
||||
buffer_read_ptr,
|
||||
buf_rdata_i,
|
||||
buf_rdata_q);
|
||||
$display("[MULTI_SEG_FIXED] Processing seg=%0d [%0d/%0d]: ADC I=%h Q=%h",
|
||||
current_segment, samples_fed, BUFFER_SIZE,
|
||||
buf_rdata_i, buf_rdata_q);
|
||||
`endif
|
||||
end
|
||||
|
||||
// Present NEXT read address (for next cycle)
|
||||
buf_raddr <= buffer_read_ptr[10:0] + 11'd1;
|
||||
buffer_read_ptr <= buffer_read_ptr + 1;
|
||||
|
||||
end else if (buffer_read_ptr >= BUFFER_SIZE) begin
|
||||
// Done feeding buffer
|
||||
fft_input_valid <= 0;
|
||||
mem_request <= 0;
|
||||
|
||||
// Present NEXT read address for next cycle.
|
||||
buf_raddr <= buffer_read_ptr + 1;
|
||||
buffer_read_ptr <= buffer_read_ptr + 1;
|
||||
samples_fed <= samples_fed + 1;
|
||||
|
||||
end else if (samples_fed >= BUFFER_SIZE) begin
|
||||
// Done feeding this segment.
|
||||
fft_input_valid <= 0;
|
||||
mem_request <= 0;
|
||||
buffer_processing <= 0;
|
||||
buffer_has_data <= 0;
|
||||
saw_chain_output <= 0;
|
||||
state <= ST_WAIT_FFT; // CRITICAL: Wait for FFT completion
|
||||
|
||||
saw_chain_output <= 0;
|
||||
state <= ST_WAIT_FFT;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Finished feeding %d samples to FFT, waiting...",
|
||||
BUFFER_SIZE);
|
||||
$display("[MULTI_SEG_FIXED] Finished feeding %0d samples for seg=%0d, waiting on FFT chain",
|
||||
BUFFER_SIZE, current_segment);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
@@ -449,56 +418,22 @@ always @(posedge clk or negedge reset_n) begin
|
||||
end
|
||||
|
||||
ST_NEXT_SEGMENT: begin
|
||||
// Prepare for next segment with OVERLAP-SAVE
|
||||
// Bump segment counter and slide the read window forward by
|
||||
// SEGMENT_ADVANCE. Buffer is stable across segments, so we
|
||||
// go straight to ST_WAIT_REF for the next reference window.
|
||||
current_segment <= current_segment + 1;
|
||||
segment_done <= 0;
|
||||
|
||||
if (is_long) begin
|
||||
// OVERLAP-SAVE: Write cached tail samples back to BRAM [0..127]
|
||||
overlap_copy_count <= 0;
|
||||
state <= ST_OVERLAP_COPY;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Overlap-save: writing %d cached samples",
|
||||
OVERLAP_SAMPLES);
|
||||
`endif
|
||||
end else begin
|
||||
// SHORT or MEDIUM: only one segment, no overlap-save.
|
||||
buffer_write_ptr <= 0;
|
||||
if (!chirp_complete) begin
|
||||
state <= ST_COLLECT_DATA;
|
||||
end else begin
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
segment_offset <= segment_offset + SEGMENT_ADVANCE;
|
||||
segment_done <= 0;
|
||||
segment_request <= current_segment + 1;
|
||||
mem_request <= 1;
|
||||
state <= ST_WAIT_REF;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Next segment: %0d (offset will be %0d)",
|
||||
current_segment + 1, segment_offset + SEGMENT_ADVANCE);
|
||||
`endif
|
||||
end
|
||||
|
||||
ST_OVERLAP_COPY: begin
|
||||
// Write one cached overlap sample per cycle to BRAM
|
||||
buf_we <= 1;
|
||||
buf_waddr <= {{3{1'b0}}, overlap_copy_count};
|
||||
buf_wdata_i <= overlap_cache_i[overlap_copy_count];
|
||||
buf_wdata_q <= overlap_cache_q[overlap_copy_count];
|
||||
|
||||
if (overlap_copy_count < OVERLAP_SAMPLES - 1) begin
|
||||
overlap_copy_count <= overlap_copy_count + 1;
|
||||
end else begin
|
||||
// All 128 samples written back
|
||||
buffer_write_ptr <= OVERLAP_SAMPLES;
|
||||
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Overlap-save: copied %d samples, write_ptr=%d",
|
||||
OVERLAP_SAMPLES, OVERLAP_SAMPLES);
|
||||
`endif
|
||||
|
||||
if (!chirp_complete) begin
|
||||
state <= ST_COLLECT_DATA;
|
||||
end else begin
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
default: begin
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
|
||||
@@ -40,7 +40,7 @@ module tb_mf_long_chirp;
|
||||
localparam SHORT_LEN = 100; // RP_DEF_SHORT_CHIRP_CYCLES_V2
|
||||
localparam MEDIUM_LEN = 500; // RP_DEF_MEDIUM_CHIRP_CYCLES
|
||||
localparam LONG_LEN = `RP_LONG_CHIRP_SAMPLES_3KM; // 3000
|
||||
localparam HARD_BUDGET_CYCLES = 200_000;
|
||||
localparam HARD_BUDGET_CYCLES = 500_000;
|
||||
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
|
||||
Reference in New Issue
Block a user