fix(mcu): P-5 — align radar params with PR-F/PR-Q.1; document mode-01 production stance

main.cpp pre-PR-F constants caused two issues:
  - m_max = 32 disagreed with RP_CHIRPS_PER_FRAME = 48 (3 sub-frames * 16);
    getStatusString reported "32 chirps/position" to the GUI, false telemetry.
  - PRI MEDIUM = 161 us (PR-Q.1 stagger) was missing entirely; the MCU only
    knew SHORT=175 / LONG=167. T2 was also stuck at the pre-PR-E 0.5 us
    SHORT chirp width; PR-E switched to 1.0 us.

Fixes:
  - m_max 32 -> 48; T2 0.5 -> 1.0; new T_MEDIUM=5.0, PRI_MEDIUM=161.0 constants.
  - Big doc-comment above runRadarPulseSequence states the production stance:
    FPGA cold-resets to mode 2'b01 (auto-scan) so the MCU's chirp GPIO toggles
    are no-ops; pass-through mode 2'b00 needs a 3-PRI loop the MCU does not
    yet emit, so mode-00 is operationally unsupported until that's built.
  - Removed the redundant /* */ block-comment shadow of the same constants
    that had `T2` defined twice (typo for `PRI2`); pure dead-code cleanup.
  - test_bug16_runradar_shadows_globals.c m_max 32 -> 48 with refreshed
    arithmetic comment; binary still PASSes all 4 checks (g_m wraps to 1
    each iter regardless of m_max value).

No GPIO timing change (would need hardware verification). Audit P-5 closes
with the documented mode-01 stance; rebuilding the loop for mode-00 stays
on the backlog if/when pass-through becomes a deployment requirement.

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -192,13 +192,19 @@ extern uint8_t GUI_start_flag_received;  // [STM32-006] Legacy, unused -- kept f
 
 
 //RADAR
-// Radar parameters
-const int m_max = 32;  // Number of chirps per beam position
+// Radar parameters — match the FPGA chirp_scheduler defaults defined in
+// 9_Firmware/9_2_FPGA/radar_params.vh (RP_DEF_*_CHIRP/LISTEN_CYCLES_V2).
+// PR-F: 48 chirps/frame = 3 sub-frames * 16 chirps each (SHORT/MEDIUM/LONG).
+// PR-Q.1: MEDIUM PRI staggered to 161 us so the 3 PRIs share no small
+// common period (175/161/167) — needed by the host CRT Doppler unfolder.
+const int m_max = 48;   // Chirps per frame (PR-F: 3 sub-frames * 16)
 const int n_max = 31;   // Number of beam positions
-const float T1 = 30.0f; // Chirp duration in microseconds
-const float PRI1 = 167.0f; // Pulse repetition interval in microseconds
-const float T2 = 0.5f;  // Short chirp duration in microseconds
-const float PRI2 = 175.0f; // Short PRI in microseconds
+const float T1 = 30.0f;     // LONG chirp duration in microseconds
+const float PRI1 = 167.0f;  // LONG PRI in microseconds
+const float T2 = 1.0f;      // SHORT chirp duration (PR-E: 0.5 us -> 1.0 us at 100 MHz)
+const float PRI2 = 175.0f;  // SHORT PRI in microseconds
+const float T_MEDIUM = 5.0f;     // MEDIUM chirp duration (PR-F)
+const float PRI_MEDIUM = 161.0f; // MEDIUM PRI (PR-Q.1 stagger)
 const float Guard = 175.4f; // Guard time in microseconds
 
 uint8_t	m = 1; // m = N° of chirp/ position = 16 (made of T1 and PRF1)+ Guard = 175µs +16 (made of T2 and PRF2)
@@ -245,15 +251,6 @@ static uint8_t matrix1[15][16];
 static uint8_t matrix2[15][16];
 static uint8_t vector_0[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
 
-/* Radar parameters
-const int m_max = 32;  // Number of chirps per beam position
-const int n_max = 31;   // Number of beam positions
-const float T1 = 30.0f; // Chirp duration in microseconds
-const float PRI1 = 167.0f; // Pulse repetition interval in microseconds
-const float T2 = 0.5f;  // Short chirp duration in microseconds
-const float T2 = 175.0f; // Short PRI in microseconds
-const float Guard = 175.40f; // Guard time in microseconds*/
-
 //Temperature Sensors
 ADS7830_HandleTypeDef hadc3;
 float Temperature_1 = 0.0f, Temperature_2 = 0.0f, Temperature_3 = 0.0f, Temperature_4 = 0.0f;
@@ -527,6 +524,26 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
     }
 }
 
+/* runRadarPulseSequence — beam-steering loop + STM32 pass-through GPIO toggles.
+ *
+ * IMPORTANT (P-5 / PR-Q.1 follow-up): in production the FPGA cold-resets to
+ * host_radar_mode = 2'b01 (auto-scan) — see radar_system_top.v:1045. In that
+ * mode the FPGA's chirp_scheduler owns chirp timing and IGNORES the GPIOD_8
+ * (new_chirp), GPIOD_9 (new_elevation), GPIOD_10 (new_azimuth) toggles this
+ * function emits via executeChirpSequence. The MCU's only live job per frame
+ * is therefore beam steering (ADAR1000 pattern updates) + stepper rotation.
+ *
+ * MODE 2'b00 (STM32 pass-through) requires the MCU to drive the 3-PRI ladder
+ *   SHORT  175 us  (T2=1 us chirp)
+ *   MEDIUM 161 us  (T_MEDIUM=5 us chirp)  -- PR-Q.1 stagger
+ *   LONG   167 us  (T1=30 us chirp)
+ * for the host-side CRT Doppler unfolder (processing.py extract_targets_from_
+ * frame_crt) to deliver unambiguous velocities. The current GPIO loop only
+ * emits two PRIs (PRI1=167 LONG, PRI2=175 SHORT) and is structured around
+ * the pre-PR-F m_max=32 frame, so pass-through mode is OPERATIONALLY
+ * UNSUPPORTED until this loop is rebuilt to dispatch 3 sub-frames in
+ * SHORT/MEDIUM/LONG order. Do not switch the FPGA into mode 00 until then.
+ */
 void runRadarPulseSequence() {
     static int sequence_count = 0;
     char msg[50];

9_Firmware/9_1_Microcontroller/tests/test_bug16_runradar_shadows_globals.c

@@ -20,8 +20,9 @@
 #include <stdio.h>
 #include <stdint.h>
 
-/* Match main.cpp lines 182-183, 190-193 */
-static const int m_max = 32;
+/* Mirror main.cpp m_max/n_max (P-5 update: m_max 32 -> 48 to match
+ * RP_CHIRPS_PER_FRAME = 48 = 3 sub-frames * 16 chirps from PR-F). */
+static const int m_max = 48;
 static const int n_max = 31;
 
 static uint8_t g_m;
@@ -101,8 +102,8 @@ int main(void)
         printf("PASS: g_n advanced to 16 after 15 beam positions\n");
     }
 
-    /* m: each iter adds 3*(m_max/2)=48; reset to 1 when m>m_max=32.
-     * 1+48=49 -> reset to 1. So after every iter m=1. */
+    /* m: each iter adds 3*(m_max/2)=72; reset to 1 when m>m_max=48.
+     * 1+72=73 -> reset to 1. So after every iter m=1. */
     if (g_m != 1) {
         fprintf(stderr, "FAIL: g_m=%u (expected 1 after wrap)\n", g_m);
         failures++;