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Two independent root causes landed together in the recent develop merge
burst, leaving CI red on every commit since. Both fixes are narrow parser/
config updates; no code logic changes.
1. Ruff T201 violation in 8_Utils/Python/LUT.py:24
The recent restoration of `print(f"8'd{val},")` (replacing `pass`) made
the LUT generator functional again, but the file is not in pyproject's
per-file-ignores so ruff's T20 rule flags it. Add a narrow per-file-
ignore for T20 specifically scoped to LUT.py.
2. Five tests in TestTier1Adar1000ChannelRegisterRoundTrip
The recent SPI/ADC error-propagation refactor on ADAR1000_Manager.cpp
changed the four setters adarSet{Rx,Tx}{Phase,VgaGain} from `void` to
`bool` returns AND introduced the `ok = setter(args) && ok` error-chain
idiom at internal call sites. The test class's parser regexes were
authored for the pre-refactor convention.
Two regex extensions:
* Body parser: `void\s+...` -> `(?:void|bool)\s+...` so bodies are
found under either return-type convention.
* Caller finder: `\)\s*;` -> `\)(?:\s*&&\s*\w+)*\s*;` so the
error-chain idiom is matched alongside standalone calls.
Body extraction logic, REG_CHn_XXX + <expr> regex, symbolic AST
evaluation, round-trip strict-equality, and stride detection are all
unchanged. The two regex extensions only acknowledge the new C++
conventions introduced by the SPI/ADC refactor.
Verified locally:
- `uv run ruff check .` returns 0 errors.
- `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py`
passes 51 tests + 5 skipped (Tier2VerilogCosim local-only, requires
iverilog which is installed in CI).
- `uv run pytest 9_Firmware/9_3_GUI/test_v7.py` passes 83 tests + 3
skipped (no regression).
55 lines
2.4 KiB
TOML
55 lines
2.4 KiB
TOML
[project]
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name = "aeris-10-radar"
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version = "1.0.0"
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description = "AERIS-10 FMCW Radar Platform — host software & FPGA cosim tools"
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requires-python = ">=3.12"
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# Runtime dependencies intentionally empty — GUI deps are optional and
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# listed in requirements_*.txt files for local installs.
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dependencies = []
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[dependency-groups]
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dev = [
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"ruff>=0.5",
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"pytest>=8",
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"numpy>=1.26",
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"h5py>=3.10",
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]
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# ---------------------------------------------------------------------------
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# Ruff configuration
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# ---------------------------------------------------------------------------
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[tool.ruff]
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target-version = "py312"
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line-length = 100
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[tool.ruff.lint]
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select = [
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"E", # pycodestyle errors
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"F", # pyflakes (unused imports, undefined names, duplicate keys, assert-tuple)
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"B", # flake8-bugbear (mutable defaults, unreachable code, raise-without-from)
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"RUF", # ruff-specific (unused noqa, ambiguous chars, implicit Optional)
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"SIM", # flake8-simplify (dead branches, collapsible ifs, unnecessary pass)
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"PIE", # flake8-pie (no-op expressions, unnecessary spread)
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"T20", # flake8-print (stray print() calls — LLMs leave debug prints)
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"ARG", # flake8-unused-arguments (LLMs generate params they never use)
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"ERA", # eradicate (commented-out code — LLMs leave "alternatives" as comments)
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"A", # flake8-builtins (LLMs shadow id, type, list, dict, input, map)
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"BLE", # flake8-blind-except (bare except / overly broad except)
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"RET", # flake8-return (unreachable code after return, unnecessary else-after-return)
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"ISC", # flake8-implicit-str-concat (missing comma in list of strings)
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"TCH", # flake8-type-checking (imports only used in type hints — move behind TYPE_CHECKING)
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"UP", # pyupgrade (outdated syntax for target Python version)
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"C4", # flake8-comprehensions (unnecessary list/dict calls around generators)
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"PERF", # perflint (performance anti-patterns: unnecessary list() in for loops, etc.)
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]
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[tool.ruff.lint.per-file-ignores]
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# Tests: allow unused args (fixtures), prints (debugging), commented code (examples)
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"test_*.py" = ["ARG", "T20", "ERA"]
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# Re-export modules: unused imports are intentional
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"v7/hardware.py" = ["F401"]
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# 8_Utils/Python/LUT.py is a single-purpose Verilog LUT generator whose only
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# output is `print(f"8'd{val},")` per the file's docstring intent.
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"8_Utils/Python/LUT.py" = ["T20"]
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