Jason 0b2f75620e perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total) ...

Re-group the 32-tap symmetric lowpass into 16 (D+A)*B operations using
the DSP48E1 pre-adder, exploiting coeff[k] == coeff[31-k]. Production
silicon (XC7A50T) drops from 112/120 DSPs (93.3%) to 80/120 (66.7%),
freeing the budget needed for the matched-filter FFT swap (RX-NEW-3).

Bit-exact contract preserved at non-saturating signal levels: DC=5000
→ 8847 and 45 MHz tone → ±16 LSB match the unfolded design and the
Python golden model. Throughput unchanged (1 sample/cycle, 100 MSPS);
latency +2 cycles for the pre-adder stage.

Saturation thresholds rebuilt via bit concatenation to dodge the
Verilog 32-bit-literal trap (1 <<< 34 silently wraps to 0, which
made the earlier symmetric draft assert positive saturation on all
non-negative accumulator values).

Local regression: 32/34 PASS — same as baseline; the two failures
(Receiver Integration, Matched Filter Chain) are pre-existing
RX-NEW-3 (FFT throughput) and unaffected by this change.

2026-04-23 10:08:19 +05:45

..

9_1_Microcontroller

fix: MCU-N4 delay_us bound; GUI-S4 STREAM_CONTROL comment

2026-04-23 07:43:53 +05:45

9_2_FPGA

perf(fpga): symmetric pre-adder FIR — 32→16 DSPs/channel (-32 total)

2026-04-23 10:08:19 +05:45

9_3_GUI

fix: MCU-N4 delay_us bound; GUI-S4 STREAM_CONTROL comment

2026-04-23 07:43:53 +05:45

tests/cross_layer

fix(radar): RX chain corrections, GUI bin alignment, MCU boot ordering

2026-04-23 05:56:52 +05:45

tools

fix: enforce strict ruff lint (17 rule sets) across entire repo

2026-04-12 14:21:03 +05:45