Re-group the 32-tap symmetric lowpass into 16 (D+A)*B operations using
the DSP48E1 pre-adder, exploiting coeff[k] == coeff[31-k]. Production
silicon (XC7A50T) drops from 112/120 DSPs (93.3%) to 80/120 (66.7%),
freeing the budget needed for the matched-filter FFT swap (RX-NEW-3).
Bit-exact contract preserved at non-saturating signal levels: DC=5000
→ 8847 and 45 MHz tone → ±16 LSB match the unfolded design and the
Python golden model. Throughput unchanged (1 sample/cycle, 100 MSPS);
latency +2 cycles for the pre-adder stage.
Saturation thresholds rebuilt via bit concatenation to dodge the
Verilog 32-bit-literal trap (1 <<< 34 silently wraps to 0, which
made the earlier symmetric draft assert positive saturation on all
non-negative accumulator values).
Local regression: 32/34 PASS — same as baseline; the two failures
(Receiver Integration, Matched Filter Chain) are pre-existing
RX-NEW-3 (FFT throughput) and unaffected by this change.
Jason
0b2f75620e