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PLFM_RADAR/9_Firmware/9_2_FPGA/tb
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Jason af64b0952e fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O 
PR-O in 8541443 packed cfg_tdata using PG109 Burst I/O semantics (22-bit
SCALE_SCH, 24-bit total). The xfft_2048 IP we instantiate is Pipelined
Streaming I/O — that arch has SCALE_SCH width = 2*ceil(NFFT_MAX/2) = 12
bits, cfg_tdata = 16 bits. Mismatch surfaced when the Vivado-regenerated
.xci reported C_S_AXIS_CONFIG_TDATA_WIDTH=16. Realigns wrappers + TBs.

Total /N scaling preserved: 22'h155555 (/N as 11 stages of >>1) becomes
12'hAA9 (stage 1 alone >>1 + stages 2-11 grouped as 5 pairs of >>2 each).
Iverilog fft_engine.v fallback unchanged — applies fixed >>>1 per stage.

Verified: tb_fft_engine_axi_bridge 4/4, tb_matched_filter_processing_chain
40/40. Vivado .dcp / .veo regenerated from .xci; gitignored as usual.
2026-05-02 10:08:00 +05:45
..
cosim
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
golden
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
ad9484_interface_400m_stub.v
fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR
2026-05-01 23:12:55 +05:45
cic_dc_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_impulse_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_sine_passband.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
ddc_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
fir_dc_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_impulse_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_sine_passband.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
gen_mf_golden_ref.py
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_out_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_ref_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_i_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case1.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case2.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case3.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_sig_q_case4.hex
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_golden_summary.txt
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
mf_pipeline_output.csv
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
nco_1mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_freq_switch.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_quadrature.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
radar_system_tb.v
chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment
2026-05-01 04:35:08 +05:45
tb_ad9484_xsim.v
fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR
2026-05-01 23:12:55 +05:45
tb_adc_pwdn_opcode.v
fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)
2026-04-29 19:37:37 +05:45
tb_audit_c16_num_cells.v
AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T
2026-04-29 23:01:41 +05:45
tb_audit_s10_gpio_split.v
fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)
2026-04-29 20:06:52 +05:45
tb_cdc_async_fifo.v
AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO
2026-04-30 10:47:31 +05:45
tb_cdc_modules.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_cfar_ca.v
chirp-v2 PR-F: doppler/CFAR widen to 3 sub-frames + 2-class detect
2026-05-01 03:36:03 +05:45
tb_chirp_contract.v
chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO
2026-04-30 21:51:46 +05:45
tb_chirp_controller.v
chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO
2026-04-30 21:51:46 +05:45
tb_cic_decimator.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ddc_400m.v
fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33
2026-04-29 14:18:25 +05:45
tb_ddc_cosim.v
fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33
2026-04-29 14:18:25 +05:45
tb_ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
tb_doppler_cosim.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_doppler_frame_start_gate.v
chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment
2026-05-01 04:35:08 +05:45
tb_doppler_realdata.v
test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures
2026-05-01 14:26:54 +05:45
tb_edge_detector.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_fft_engine_axi_bridge.v
fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O
2026-05-02 10:08:00 +05:45
tb_fft_engine.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_fir_lowpass.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_fpga_self_test.v
AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic
2026-04-29 23:27:15 +05:45
tb_freq_matched_filter.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ft2232h_frame_drop.v
chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder
2026-05-01 11:10:06 +05:45
tb_fullchain_realdata.v
test(realdata): PR-K — synthetic regen of doppler/fullchain realdata fixtures
2026-05-01 14:26:54 +05:45
tb_matched_filter_processing_chain.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_mf_cosim.v
cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain
2026-04-27 14:06:55 +05:45
tb_mf_long_chirp.v
fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)
2026-05-01 15:07:19 +05:45
tb_mti_canceller.v
chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native
2026-04-30 20:52:32 +05:45
tb_multiseg_cosim.v
chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native
2026-04-30 20:52:32 +05:45
tb_nco_400m.v
fix(fpga): pre-bringup RTL hardening + test-suite hardening
2026-04-22 13:23:38 +05:45
tb_nco_xsim.v
Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization
2026-03-16 23:23:06 +02:00
tb_radar_receiver_final.v
chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment
2026-05-01 04:35:08 +05:45
tb_range_bin_decimator.v
merge(wave3/tier2): port testbenches and cosim goldens for fft-2048
2026-04-21 03:04:52 +05:45
tb_rx_gain_control.v
fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes
2026-04-13 23:35:10 +05:45
tb_rxb_fullchain_latency.v
fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening
2026-05-02 08:33:06 +05:45
tb_rxb_latency_measure.v
cleanup(fpga): RX-A1 — drop dead chirp_counter port from MF chain
2026-04-27 14:06:55 +05:45
tb_system_dataflow.v
test(dataflow): PR-I.3 — tb_system_dataflow shallow integration probe
2026-05-01 12:50:28 +05:45
tb_system_mechanics.v
test(mechanics): PR-I.2 — tb_system_mechanics for chirp/RF/safety/CDC
2026-05-01 12:10:23 +05:45
tb_system_opcodes.v
test(opcodes): PR-I.1 — tb_system_opcodes via production FT2232H path
2026-05-01 12:07:31 +05:45
tb_threshold_detector.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_usb_data_interface.v
AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T
2026-04-29 23:01:41 +05:45
tb_usb_protocol_v2.v
test(integration): PR-I.4 — wire new TBs into regression, retire tb_system_e2e
2026-05-01 13:37:16 +05:45
tb_xfft_2048_xsim.v
fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O
2026-05-02 10:08:00 +05:45