Jason 7ed4d5d405 test(fpga): PR-Q.2 — align cosim T_PRI_MEDIUM 175->161 us + regen goldens ...

Mirror the PR-Q.1 PRI stagger (MEDIUM 175 us -> 161 us) into the cosim
scenario generator and regenerate all 12 affected golden hex/csv files.
Without this, the Doppler co-sim TBs would diverge from the RTL on every
MEDIUM sub-frame bin.

- tb/cosim/radar_scene.py: T_PRI_MEDIUM = 161e-6
- tb/cosim/gen_doppler_golden.py: comment update for MEDIUM bin map
- 12 regenerated hex/csv files (doppler + real_data + fullchain_realdata)

Regression: 42/0/1 (PR-Q.1 baseline preserved; T-6 SKIP is scipy-missing).

2026-05-02 14:33:23 +05:45

..

constraints

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

formal

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

ip/xfft_2048_ip

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

scripts

test(fpga): xsim runner for tb_matched_filter_processing_chain

2026-05-02 11:16:17 +05:45

tb

test(fpga): PR-Q.2 — align cosim T_PRI_MEDIUM 175->161 us + regen goldens

2026-05-02 14:33:23 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

adc_clk_mmcm_integration.md

Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix

2026-03-19 22:59:46 +02:00

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

docs(cfar): PR-M.4 — note Doppler-window dependency on CFAR alpha

2026-05-01 18:53:24 +05:45

chirp_reference_rom.v

chirp-v2 PR-C: chirp_reference_rom replaces chirp_memory_loader_param

2026-04-30 19:37:43 +05:45

chirp_scheduler.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

edge_detector.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

fft_engine_axi_bridge.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

fft_engine.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

fft_twiddle_16.mem

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

AUDIT-S17: document fir_lowpass +4.96 dB DC gain and CIC-droop comp

2026-04-30 10:08:34 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

matched_filter_multi_segment.v

fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)

2026-05-01 15:07:19 +05:45

matched_filter_processing_chain.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller_v2.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

radar_params.vh

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_receiver_final.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

radar_system_top_50t.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

radar_system_top_te0712_dev.v

Add TE0712/TE0701 split target with dedicated top, XDC, and build flow

2026-03-18 03:57:26 +02:00

radar_system_top_te0713_dev.v

Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

2026-03-19 16:47:59 +02:00

radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_transmitter.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

ci(fpga): PR-M.3 — wire T-6 drift cosim into regression + CI deps

2026-05-01 18:53:09 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

rx_long_seg0_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg0_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_long_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_medium_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_short_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

usb_data_interface_ft2232h.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

xfft_2048.v

fix(fpga): PR-O.8.1 — drop stale BFP-era ports, fix xsim include path

2026-05-02 10:20:10 +05:45