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qla2x00t: New version with 16G support (merge r6148 from trunk)

Browse Source 
git-svn-id: http://svn.code.sf.net/p/scst/svn/branches/3.0.x@6291 d57e44dd-8a1f-0410-8b47-8ef2f437770f
This commit is contained in:
Bart Van Assche
2015-06-11 17:30:30 +00:00
parent 9b5582cf90
commit 6318e46e55
32 changed files with 27460 additions and 7976 deletions
Download Patch File Download Diff File Expand all files Collapse all files
qla2x00t/Makefile
+2 -2
View File
@@ -1,7 +1,7 @@
ifeq ($(BUILD_2X_MODULE),)
qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o
qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o qla_nx.o
obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx.o
@@ -53,7 +53,7 @@ INSTALL_DIR := $(INSTALL_MOD_PATH)/lib/modules/$(KVER)/extra
ifneq ($(PATCHLEVEL),)
obj-m := qla2xxx_scst.o
qla2xxx_scst-objs := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o
qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o qla_nx.o
else
all:
qla2x00t/qla2x00-target/ChangeLog
+9 -1
View File
@@ -1,7 +1,15 @@
Summary of changes between versions 3.0 and 3.1
-----------------------------------------------
- Support for 26xx/8[1-3]xx added
- Update to a newer qla2xxx
Summary of changes between versions 2.1.0 and 3.0
-------------------------------------------------
- Update to kernels up to 3.3
- Update to kernels up to 3.6
- Bug fixes and other improvements
qla2x00t/qla2x00-target/README
+3 -14
View File
@@ -1,5 +1,5 @@
Target driver for QLogic 22xx/23xx/24xx/25xx Fibre Channel cards
================================================================
Target driver for QLogic 2[2-6]xx/8[1-3]xx Fibre Channel cards
==============================================================
Version 3.0.2, XXX 2015
-----------------------
@@ -12,22 +12,11 @@ necessary callbacks, but it's still capable to work as initiator only.
Mode, when a host acts as the initiator and the target simultaneously,
is supported as well.
This version is compatible with SCST core version 2.0.0 and higher and
This version is compatible with SCST core version 3.1.0 and higher and
Linux kernel 2.6.26 and higher. Sorry, kernels below 2.6.26 are not
supported, because it's too hard to backport used initiator driver to
older kernels.
The original initiator driver was taken from the kernel 2.6.26. Also the
following 2.6.26+ commits have been applied to it (upstream ID):
048feec5548c0582ee96148c61b87cccbcb5f9be,
031e134e5f95233d80fb1b62fdaf5e1be587597c,
5f3a9a207f1fccde476dd31b4c63ead2967d934f,
85821c906cf3563a00a3d98fa380a2581a7a5ff1,
3c01b4f9fbb43fc911acd33ea7a14ea7a4f9866b,
8eca3f39c4b11320787f7b216f63214aee8415a9,
0f19bc681ed0849a2b95778460a0a8132e3700e2,
a55aac79de0ea6fc52d35f535867b6573a5ff0f8.
See also "ToDo" file for list of known issues and unimplemented
features.
qla2x00t/qla2x00-target/ToDo
+4 -2
View File
@@ -1,10 +1,12 @@
Known issues and unimplemented features
---------------------------------------
- Allow to set port names through sysfs.
- NPIV targets not quite work. If you need NPIV, use QLogic git driver
- Minor "ToDo"'s spread in the code.
Very old and, probably, already fixed:
- If a Linux initiator asks for devices using INQUIRY command too soon
before the controller on the 23xx target is fully initialized in the
target mode, the initiator could receive garbage devices and the
qla2x00t/qla2x00-target/V2_RELEASE_NOTES
-29
View File
@@ -1,29 +0,0 @@
Throughout the last three years ID7 and I have been working on an
enterprise class Fibre Channel target based on the QLogic range of 4/8Gb
HBA's. This has been solely funded by ID7 over the last years however
given the positive contributions by many of the SCST community both
personal and commercial, ID7 have chosen to merge with existing QLogic's
open source driver qla2x00t and introduce the driver under GPL license
for community use.
This driver was designed from ground up to perform at the highest of
levels and interoperate with leading infrastructures, accordingly the
design and flow is much more focused and structured whilst the stability
is as you would expect at the Enterprise level.
Although there is a current QLogic target driver qla_isp, this driver
has the key advantage that it was designed to be as simple as possible.
As the result, this driver is a lot smaller, cleaner and mainline Linux
kernel ready. It's going to be pushed for the in-kernel inclusion
together other SCST patches.
Another advantage is that this driver fully supports FC tapes, including
transport level retries on data delivery problems.
Once again we are grateful for all the positive work and contributions
and hopeful that this target helps drive SCST further forward as an
Enterprise class target. We encourage people to introduce and evaluate
this target driver.
Vladislav Bolkhovitin,
Mark Klarzynski, ID7 Ltd. (http://www.id-7.com)
qla2x00t/qla2x00-target/qla2x00t.c
+1301 -964
View File
File diff suppressed because it is too large Load Diff
qla2x00t/qla2x00-target/qla2x00t.h
+15 -12
View File
@@ -30,7 +30,7 @@
/* Version numbers, the same as for the kernel */
#define Q2T_VERSION(a, b, c, d) (((a) << 030) + ((b) << 020) + (c) << 010 + (d))
#define Q2T_VERSION_CODE Q2T_VERSION(3, 0, 1, 0)
#define Q2T_VERSION_CODE Q2T_VERSION(3, 0, 2, 0)
#define Q2T_VERSION_STRING "3.0.2"
#define Q2T_PROC_VERSION_NAME "version"
@@ -47,7 +47,7 @@
#define IMM_NTFY_PORT_LOGOUT 0x0029
#define IMM_NTFY_PORT_CONFIG 0x002A
#define IMM_NTFY_GLBL_TPRLO 0x002D
#define IMM_NTFY_GLBL_LOGO 0x002E
#define IMM_NTFY_LINK_FAILURE 0x002E
#define IMM_NTFY_RESOURCE 0x0034
#define IMM_NTFY_MSG_RX 0x0036
#define IMM_NTFY_SRR 0x0045
@@ -114,7 +114,7 @@
struct q2t_tgt {
struct scst_tgt *scst_tgt;
scsi_qla_host_t *ha;
scsi_qla_host_t *vha;
/*
* To sync between IRQ handlers and q2t_target_release(). Needed,
@@ -125,8 +125,7 @@ struct q2t_tgt {
int datasegs_per_cmd, datasegs_per_cont;
/* Target's flags, serialized by pha->hardware_lock */
unsigned int tgt_enable_64bit_addr:1; /* 64-bits PCI addressing enabled */
/* Target's flags, serialized by ha->hardware_lock */
unsigned int link_reinit_iocb_pending:1;
unsigned int tm_to_unknown:1; /* TM to unknown session was sent */
unsigned int sess_works_pending:1; /* there are sess_work entries */
@@ -137,17 +136,17 @@ struct q2t_tgt {
*/
unsigned long tgt_stop; /* the driver is being stopped */
struct work_struct rscn_reg_work;
/* Count of sessions referring q2t_tgt. Protected by hardware_lock. */
int sess_count;
/*
* Protected by hardware_lock. Adding new sessions (not undelete)
* also protected by tgt_mutex.
*/
struct list_head sess_list;
struct work_struct rscn_reg_work;
/* Count of sessions referring q2t_tgt. Protected by hardware_lock. */
int sess_count;
/* Protected by hardware_lock */
struct list_head del_sess_list;
struct delayed_work sess_del_work;
@@ -170,8 +169,6 @@ struct q2t_tgt {
struct work_struct srr_work;
atomic_t tgt_global_resets_count;
struct list_head tgt_list_entry;
};
/*
@@ -226,6 +223,12 @@ struct q2t_cmd {
struct scst_cmd scst_cmd;
};
struct q2t_unknown_atio {
atio7_entry_t atio7;
scsi_qla_host_t *vha;
struct list_head unknown_atio_list_entry;
};
struct q2t_sess_work_param {
struct list_head sess_works_list_entry;
qla2x00t/qla2x_tgt.h
+48 -25
View File
@@ -28,7 +28,7 @@
#include <linux/version.h>
extern request_t *qla2x00_req_pkt(scsi_qla_host_t *ha);
extern request_t *qla2x00_req_pkt(scsi_qla_host_t *vha);
#ifdef CONFIG_SCSI_QLA2XXX_TARGET
@@ -36,25 +36,25 @@ extern request_t *qla2x00_req_pkt(scsi_qla_host_t *ha);
extern struct qla_tgt_data qla_target;
void qla_set_tgt_mode(scsi_qla_host_t *ha);
void qla_clear_tgt_mode(scsi_qla_host_t *ha);
void qla_set_tgt_mode(scsi_qla_host_t *vha);
void qla_clear_tgt_mode(scsi_qla_host_t *vha);
static inline bool qla_tgt_mode_enabled(scsi_qla_host_t *ha)
static inline bool qla_tgt_mode_enabled(scsi_qla_host_t *vha)
{
return ha->host->active_mode & MODE_TARGET;
return vha->host->active_mode & MODE_TARGET;
}
static inline bool qla_ini_mode_enabled(scsi_qla_host_t *ha)
static inline bool qla_ini_mode_enabled(scsi_qla_host_t *vha)
{
return ha->host->active_mode & MODE_INITIATOR;
return vha->host->active_mode & MODE_INITIATOR;
}
static inline void qla_reverse_ini_mode(scsi_qla_host_t *ha)
static inline void qla_reverse_ini_mode(scsi_qla_host_t *vha)
{
if (ha->host->active_mode & MODE_INITIATOR)
ha->host->active_mode &= ~MODE_INITIATOR;
if (vha->host->active_mode & MODE_INITIATOR)
vha->host->active_mode &= ~MODE_INITIATOR;
else
ha->host->active_mode |= MODE_INITIATOR;
vha->host->active_mode |= MODE_INITIATOR;
}
/********************************************************************\
@@ -72,13 +72,14 @@ static inline void qla_reverse_ini_mode(scsi_qla_host_t *ha)
* then reacquire.
*/
static inline void
__qla2x00_send_enable_lun(scsi_qla_host_t *ha, int enable)
__qla2x00_send_enable_lun(scsi_qla_host_t *vha, int enable)
{
elun_entry_t *pkt;
struct qla_hw_data *ha = vha->hw;
BUG_ON(IS_FWI2_CAPABLE(ha));
pkt = (elun_entry_t *)qla2x00_req_pkt(ha);
pkt = (elun_entry_t *)qla2x00_req_pkt(vha);
if (pkt != NULL) {
pkt->entry_type = ENABLE_LUN_TYPE;
if (enable) {
@@ -90,16 +91,16 @@ __qla2x00_send_enable_lun(scsi_qla_host_t *ha, int enable)
pkt->immed_notify_count = 0;
pkt->timeout = 0;
}
DEBUG2(printk(KERN_DEBUG
ql_dbg(ql_dbg_init, vha, 0x0077,
"scsi%lu:ENABLE_LUN IOCB imm %u cmd %u timeout %u\n",
ha->host_no, pkt->immed_notify_count,
pkt->command_count, pkt->timeout));
vha->host_no, pkt->immed_notify_count,
pkt->command_count, pkt->timeout);
/* Issue command to ISP */
qla2x00_isp_cmd(ha);
qla2x00_start_iocbs(vha, vha->req);
} else
qla_clear_tgt_mode(ha);
qla_clear_tgt_mode(vha);
#if defined(QL_DEBUG_LEVEL_2) || defined(QL_DEBUG_LEVEL_3)
if (!pkt)
pr_err("%s: **** FAILED ****\n", __func__);
@@ -117,14 +118,15 @@ __qla2x00_send_enable_lun(scsi_qla_host_t *ha, int enable)
* enable = enable/disable flag.
*/
static inline void
qla2x00_send_enable_lun(scsi_qla_host_t *ha, bool enable)
qla2x00_send_enable_lun(scsi_qla_host_t *vha, bool enable)
{
struct qla_hw_data *ha = vha->hw;
if (!IS_FWI2_CAPABLE(ha)) {
unsigned long flags;
scsi_qla_host_t *pha = to_qla_parent(ha);
spin_lock_irqsave(&pha->hardware_lock, flags);
__qla2x00_send_enable_lun(ha, enable);
spin_unlock_irqrestore(&pha->hardware_lock, flags);
spin_lock_irqsave(&ha->hardware_lock, flags);
__qla2x00_send_enable_lun(vha, enable);
spin_unlock_irqrestore(&ha->hardware_lock, flags);
}
}
@@ -132,11 +134,32 @@ extern void qla2xxx_add_targets(void);
#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) || \
defined(FC_VPORT_CREATE_DEFINED))
extern size_t
qla2xxx_add_vtarget(u64 *port_name, u64 *node_name, u64 *parent_host);
extern size_t qla2xxx_del_vtarget(u64 *port_name);
qla2xxx_add_vtarget(u64 port_name, u64 node_name, u64 parent_host);
extern size_t qla2xxx_del_vtarget(u64 port_name);
#endif /*((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) || \
defined(FC_VPORT_CREATE_DEFINED))*/
extern void qla_unknown_atio_work_fn(struct delayed_work *work);
#else /* CONFIG_SCSI_QLA2XXX_TARGET */
static inline bool qla_tgt_mode_enabled(scsi_qla_host_t *vha)
{
return false;
}
static inline bool qla_ini_mode_enabled(scsi_qla_host_t *vha)
{
return true;
}
#endif /* CONFIG_SCSI_QLA2XXX_TARGET */
static inline bool qla_firmware_active(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
return qla_tgt_mode_enabled(base_vha) || qla_ini_mode_enabled(base_vha);
}
#endif /* __QLA2X_TGT_H */
qla2x00t/qla2x_tgt_def.h
+36 -32
View File
@@ -44,13 +44,13 @@
* Must be changed on any change in any initiator visible interfaces or
* data in the target add-on
*/
#define QLA2X_TARGET_MAGIC 270
#define QLA2X_TARGET_MAGIC 1377
/*
* Must be changed on any change in any target visible interfaces or
* data in the initiator
*/
#define QLA2X_INITIATOR_MAGIC 57225
#define QLA2X_INITIATOR_MAGIC 59232
#define QLA2X_INI_MODE_STR_EXCLUSIVE "exclusive"
#define QLA2X_INI_MODE_STR_DISABLED "disabled"
@@ -148,7 +148,7 @@ typedef struct {
uint16_t reserved_5;
uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
uint16_t reserved_6[20];
} __packed elun_entry_t;
} __attribute__((packed)) elun_entry_t;
#define ENABLE_LUN_SUCCESS 0x01
#define ENABLE_LUN_RC_NONZERO 0x04
#define ENABLE_LUN_INVALID_REQUEST 0x06
@@ -179,7 +179,7 @@ typedef struct {
uint16_t reserved_5;
uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
uint16_t reserved_7[20];
} __packed modify_lun_entry_t;
} __attribute__((packed)) modify_lun_entry_t;
#define MODIFY_LUN_SUCCESS 0x01
#define MODIFY_LUN_CMD_ADD BIT_0
#define MODIFY_LUN_CMD_SUB BIT_1
@@ -219,7 +219,7 @@ typedef struct {
uint16_t srr_ox_id;
uint8_t reserved_2[30];
uint16_t ox_id;
} __packed notify_entry_t;
} __attribute__((packed)) notify_entry_t;
#endif
#ifndef NOTIFY_ACK_TYPE
@@ -250,7 +250,7 @@ typedef struct {
uint8_t srr_reject_code_expl;
uint8_t reserved_2[26];
uint16_t ox_id;
} __packed nack_entry_t;
} __attribute__((packed)) nack_entry_t;
#define NOTIFY_ACK_SRR_FLAGS_ACCEPT 0
#define NOTIFY_ACK_SRR_FLAGS_REJECT 1
@@ -287,7 +287,7 @@ typedef struct {
uint8_t initiator_port_name[WWN_SIZE]; /* on qla23xx */
uint16_t reserved_32[6];
uint16_t ox_id;
} __packed atio_entry_t;
} __attribute__((packed)) atio_entry_t;
#endif
#ifndef CONTINUE_TGT_IO_TYPE
@@ -314,7 +314,7 @@ typedef struct {
uint16_t scsi_status;
uint32_t transfer_length;
uint32_t dseg_0_address[0];
} __packed ctio_common_entry_t;
} __attribute__((packed)) ctio_common_entry_t;
#define ATIO_PATH_INVALID 0x07
#define ATIO_CANT_PROV_CAP 0x16
#define ATIO_CDB_VALID 0x3D
@@ -333,7 +333,7 @@ typedef struct {
uint32_t dseg_1_length; /* Data segment 1 length. */
uint32_t dseg_2_address; /* Data segment 2 address. */
uint32_t dseg_2_length; /* Data segment 2 length. */
} __packed ctio_entry_t;
} __attribute__((packed)) ctio_entry_t;
#define CTIO_SUCCESS 0x01
#define CTIO_ABORTED 0x02
#define CTIO_INVALID_RX_ID 0x08
@@ -371,7 +371,7 @@ typedef struct {
uint16_t scsi_status;
uint16_t response_length;
uint8_t sense_data[26];
} __packed ctio_ret_entry_t;
} __attribute__((packed)) ctio_ret_entry_t;
#endif
#define ATIO_TYPE7 0x06 /* Accept target I/O entry for 24xx */
@@ -389,7 +389,7 @@ typedef struct {
uint16_t ox_id;
uint16_t rx_id;
uint32_t parameter;
} __packed fcp_hdr_t;
} __attribute__((packed)) fcp_hdr_t;
typedef struct {
uint8_t d_id[3];
@@ -404,7 +404,7 @@ typedef struct {
uint16_t rx_id;
uint16_t ox_id;
uint32_t parameter;
} __packed fcp_hdr_le_t;
} __attribute__((packed)) fcp_hdr_le_t;
#define F_CTL_EXCH_CONTEXT_RESP BIT_23
#define F_CTL_SEQ_CONTEXT_RESIP BIT_22
@@ -449,7 +449,7 @@ typedef struct {
*/
uint8_t add_cdb[4];
/* uint32_t data_length; */
} __packed fcp_cmnd_t;
} __attribute__((packed)) fcp_cmnd_t;
/*
* ISP queue - Accept Target I/O (ATIO) type 7 entry for 24xx structure
@@ -470,7 +470,7 @@ typedef struct {
#define ATIO_EXCHANGE_ADDRESS_UNKNOWN 0xFFFFFFFF
fcp_hdr_t fcp_hdr;
fcp_cmnd_t fcp_cmnd;
} __packed atio7_entry_t;
} __attribute__((packed)) atio7_entry_t;
#define CTIO_TYPE7 0x12 /* Continue target I/O entry (for 24xx) */
@@ -494,7 +494,7 @@ typedef struct {
uint8_t initiator_id[3];
uint8_t reserved;
uint32_t exchange_addr;
} __packed ctio7_common_entry_t;
} __attribute__((packed)) ctio7_common_entry_t;
typedef struct {
ctio7_common_entry_t common;
@@ -509,7 +509,7 @@ typedef struct {
uint32_t reserved3;
uint32_t dseg_0_address[2]; /* Data segment 0 address. */
uint32_t dseg_0_length; /* Data segment 0 length. */
} __packed ctio7_status0_entry_t;
} __attribute__((packed)) ctio7_status0_entry_t;
typedef struct {
ctio7_common_entry_t common;
@@ -521,7 +521,7 @@ typedef struct {
uint16_t response_len;
uint16_t reserved;
uint8_t sense_data[24];
} __packed ctio7_status1_entry_t;
} __attribute__((packed)) ctio7_status1_entry_t;
typedef struct {
uint8_t entry_type; /* Entry type. */
@@ -542,7 +542,7 @@ typedef struct {
uint16_t reserved3;
uint32_t relative_offset;
uint8_t reserved4[24];
} __packed ctio7_fw_entry_t;
} __attribute__((packed)) ctio7_fw_entry_t;
/* CTIO7 flags values */
#define CTIO7_FLAGS_SEND_STATUS BIT_15
@@ -574,19 +574,22 @@ typedef struct {
uint16_t srr_rx_id;
uint16_t status;
uint8_t status_subcode;
uint8_t reserved_3;
uint8_t fw_handle;
uint32_t exchange_address;
uint32_t srr_rel_offs;
uint16_t srr_ui;
uint16_t srr_ox_id;
uint8_t reserved_4[19];
uint8_t els_nport_id[3];
uint8_t reserved_4;
uint16_t els_nport_handle;
uint8_t reserved_5[13];
uint8_t vp_index;
uint32_t reserved_5;
uint32_t reserved_6;
uint8_t port_id[3];
uint8_t reserved_6;
uint16_t reserved_7;
uint8_t reserved_7;
uint16_t reserved_8;
uint16_t ox_id;
} __packed notify24xx_entry_t;
} __attribute__((packed)) notify24xx_entry_t;
#define ELS_PLOGI 0x3
#define ELS_FLOGI 0x4
@@ -612,7 +615,7 @@ typedef struct {
uint16_t srr_rx_id;
uint16_t status;
uint8_t status_subcode;
uint8_t reserved_3;
uint8_t fw_handle;
uint32_t exchange_address;
uint32_t srr_rel_offs;
uint16_t srr_ui;
@@ -624,7 +627,7 @@ typedef struct {
uint8_t srr_reject_code;
uint8_t reserved_5[7];
uint16_t ox_id;
} __packed nack24xx_entry_t;
} __attribute__((packed)) nack24xx_entry_t;
/*
* ISP queue - ABTS received/response entries structure definition for 24xx.
@@ -652,7 +655,7 @@ typedef struct {
fcp_hdr_le_t fcp_hdr_le;
uint8_t reserved_4[16];
uint32_t exchange_addr_to_abort;
} __packed abts24_recv_entry_t;
} __attribute__((packed)) abts24_recv_entry_t;
#define ABTS_PARAM_ABORT_SEQ BIT_0
@@ -666,7 +669,7 @@ typedef struct {
uint16_t ox_id;
uint16_t high_seq_cnt;
uint16_t low_seq_cnt;
} __packed ba_acc_le_t;
} __attribute__((packed)) ba_acc_le_t;
typedef struct {
uint8_t vendor_uniq;
@@ -675,7 +678,7 @@ typedef struct {
#define BA_RJT_REASON_CODE_INVALID_COMMAND 0x1
#define BA_RJT_REASON_CODE_UNABLE_TO_PERFORM 0x9
uint8_t reserved;
} __packed ba_rjt_le_t;
} __attribute__((packed)) ba_rjt_le_t;
typedef struct {
uint8_t entry_type; /* Entry type. */
@@ -700,10 +703,10 @@ typedef struct {
union {
ba_acc_le_t ba_acct;
ba_rjt_le_t ba_rjt;
} __packed payload;
} __attribute__((packed)) payload;
uint32_t reserved_4;
uint32_t exchange_addr_to_abort;
} __packed abts24_resp_entry_t;
} __attribute__((packed)) abts24_resp_entry_t;
typedef struct {
uint8_t entry_type; /* Entry type. */
@@ -731,7 +734,7 @@ typedef struct {
#define ABTS_RESP_SUBCODE_ERR_ABORTED_EXCH_NOT_TERM 0x1E
uint32_t error_subcode2;
uint32_t exchange_addr_to_abort;
} __packed abts24_resp_fw_entry_t;
} __attribute__((packed)) abts24_resp_fw_entry_t;
/********************************************************************\
* Type Definitions used by initiator & target halves
@@ -754,6 +757,7 @@ struct qla_tgt_data {
void (*tgt2x_ctio_completion)(scsi_qla_host_t *ha, uint32_t handle);
void (*tgt_async_event)(uint16_t code, scsi_qla_host_t *ha,
uint16_t *mailbox);
void (*tgt_try_to_dequeue_unknown_atios)(struct qla_hw_data *ha);
int (*tgt_host_action)(scsi_qla_host_t *ha, qla2x_tgt_host_action_t
action);
void (*tgt_fc_port_added)(scsi_qla_host_t *ha, fc_port_t *fcport);
qla2x00t/qla_attr.c
+1012 -567
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File diff suppressed because it is too large Load Diff
qla2x00t/qla_bsg.c
+1711
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File diff suppressed because it is too large Load Diff
qla2x00t/qla_bsg.h
+186
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@@ -0,0 +1,186 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
#ifndef __QLA_BSG_H
#define __QLA_BSG_H
/* BSG Vendor specific commands */
#define QL_VND_LOOPBACK 0x01
#define QL_VND_A84_RESET 0x02
#define QL_VND_A84_UPDATE_FW 0x03
#define QL_VND_A84_MGMT_CMD 0x04
#define QL_VND_IIDMA 0x05
#define QL_VND_FCP_PRIO_CFG_CMD 0x06
#define QL_VND_READ_FLASH 0x07
#define QL_VND_UPDATE_FLASH 0x08
#define QL_VND_SET_FRU_VERSION 0x0B
#define QL_VND_READ_FRU_STATUS 0x0C
#define QL_VND_WRITE_FRU_STATUS 0x0D
/* BSG Vendor specific subcode returns */
#define EXT_STATUS_OK 0
#define EXT_STATUS_ERR 1
#define EXT_STATUS_INVALID_PARAM 6
#define EXT_STATUS_MAILBOX 11
#define EXT_STATUS_NO_MEMORY 17
/* BSG definations for interpreting CommandSent field */
#define INT_DEF_LB_LOOPBACK_CMD 0
#define INT_DEF_LB_ECHO_CMD 1
/* Loopback related definations */
#define EXTERNAL_LOOPBACK 0xF2
#define ENABLE_INTERNAL_LOOPBACK 0x02
#define INTERNAL_LOOPBACK_MASK 0x000E
#define MAX_ELS_FRAME_PAYLOAD 252
#define ELS_OPCODE_BYTE 0x10
/* BSG Vendor specific definations */
#define A84_ISSUE_WRITE_TYPE_CMD 0
#define A84_ISSUE_READ_TYPE_CMD 1
#define A84_CLEANUP_CMD 2
#define A84_ISSUE_RESET_OP_FW 3
#define A84_ISSUE_RESET_DIAG_FW 4
#define A84_ISSUE_UPDATE_OPFW_CMD 5
#define A84_ISSUE_UPDATE_DIAGFW_CMD 6
struct qla84_mgmt_param {
union {
struct {
uint32_t start_addr;
} mem; /* for QLA84_MGMT_READ/WRITE_MEM */
struct {
uint32_t id;
#define QLA84_MGMT_CONFIG_ID_UIF 1
#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
#define QLA84_MGMT_CONFIG_ID_PAUSE 3
#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
uint32_t param0;
uint32_t param1;
} config; /* for QLA84_MGMT_CHNG_CONFIG */
struct {
uint32_t type;
#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
uint32_t context;
/*
* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
*/
#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
/*
* context definitions for QLA84_MGMT_INFO_PORT_STAT
*/
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
/*
* context definitions for QLA84_MGMT_INFO_LIF_STAT
*/
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
} info; /* for QLA84_MGMT_GET_INFO */
} u;
};
struct qla84_msg_mgmt {
uint16_t cmd;
#define QLA84_MGMT_READ_MEM 0x00
#define QLA84_MGMT_WRITE_MEM 0x01
#define QLA84_MGMT_CHNG_CONFIG 0x02
#define QLA84_MGMT_GET_INFO 0x03
uint16_t rsrvd;
struct qla84_mgmt_param mgmtp;/* parameters for cmd */
uint32_t len; /* bytes in payload following this struct */
uint8_t payload[0]; /* payload for cmd */
};
struct qla_bsg_a84_mgmt {
struct qla84_msg_mgmt mgmt;
} __attribute__ ((packed));
struct qla_scsi_addr {
uint16_t bus;
uint16_t target;
} __attribute__ ((packed));
struct qla_ext_dest_addr {
union {
uint8_t wwnn[8];
uint8_t wwpn[8];
uint8_t id[4];
struct qla_scsi_addr scsi_addr;
} dest_addr;
uint16_t dest_type;
#define EXT_DEF_TYPE_WWPN 2
uint16_t lun;
uint16_t padding[2];
} __attribute__ ((packed));
struct qla_port_param {
struct qla_ext_dest_addr fc_scsi_addr;
uint16_t mode;
uint16_t speed;
} __attribute__ ((packed));
/* FRU VPD */
#define MAX_FRU_SIZE 36
struct qla_field_address {
uint16_t offset;
uint16_t device;
uint16_t option;
} __packed;
struct qla_field_info {
uint8_t version[MAX_FRU_SIZE];
} __packed;
struct qla_image_version {
struct qla_field_address field_address;
struct qla_field_info field_info;
} __packed;
struct qla_image_version_list {
uint32_t count;
struct qla_image_version version[0];
} __packed;
struct qla_status_reg {
struct qla_field_address field_address;
uint8_t status_reg;
uint8_t reserved[7];
} __packed;
#endif
qla2x00t/qla_dbg.c
+1310 -128
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File diff suppressed because it is too large Load Diff
qla2x00t/qla_dbg.h
+169 -123
View File
@@ -1,132 +1,11 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
/*
* Driver debug definitions.
*/
/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */
/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */
/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */
/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */
/* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */
/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
/* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
/* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
/*
* Macros use for debugging the driver.
*/
#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#if defined(QL_DEBUG_LEVEL_1)
#define DEBUG1(x) do {x;} while (0)
#else
#define DEBUG1(x) do {} while (0)
#endif
#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0)
#if defined(QL_DEBUG_LEVEL_3)
#define DEBUG3(x) do {x;} while (0)
#define DEBUG3_11(x) do {x;} while (0)
#else
#define DEBUG3(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_4)
#define DEBUG4(x) do {x;} while (0)
#else
#define DEBUG4(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_5)
#define DEBUG5(x) do {x;} while (0)
#else
#define DEBUG5(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_7)
#define DEBUG7(x) do {x;} while (0)
#else
#define DEBUG7(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_9)
#define DEBUG9(x) do {x;} while (0)
#define DEBUG9_10(x) do {x;} while (0)
#else
#define DEBUG9(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_10)
#define DEBUG10(x) do {x;} while (0)
#define DEBUG9_10(x) do {x;} while (0)
#else
#define DEBUG10(x) do {} while (0)
#if !defined(DEBUG9_10)
#define DEBUG9_10(x) do {} while (0)
#endif
#endif
#if defined(QL_DEBUG_LEVEL_11)
#define DEBUG11(x) do{x;} while(0)
#if !defined(DEBUG3_11)
#define DEBUG3_11(x) do{x;} while(0)
#endif
#else
#define DEBUG11(x) do{} while(0)
#if !defined(QL_DEBUG_LEVEL_3)
#define DEBUG3_11(x) do{} while(0)
#endif
#endif
#if defined(QL_DEBUG_LEVEL_12)
#define DEBUG12(x) do {x;} while (0)
#else
#define DEBUG12(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_13)
#define DEBUG13(x) do {x;} while (0)
#else
#define DEBUG13(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_14)
#define DEBUG14(x) do {x;} while (0)
#else
#define DEBUG14(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_15)
#define DEBUG15(x) do {x;} while (0)
#else
#define DEBUG15(x) do {} while (0)
#endif
#if defined(QL_DEBUG_LEVEL_16)
#define DEBUG16(x) do {x;} while (0)
#else
#define DEBUG16(x) do {} while (0)
#endif
#include "qla_def.h"
/*
* Firmware Dump structure definition
@@ -247,6 +126,93 @@ struct qla25xx_fw_dump {
uint32_t ext_mem[1];
};
struct qla81xx_fw_dump {
uint32_t host_status;
uint32_t host_risc_reg[32];
uint32_t pcie_regs[4];
uint32_t host_reg[32];
uint32_t shadow_reg[11];
uint32_t risc_io_reg;
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[128];
uint32_t xseq_0_reg[48];
uint32_t xseq_1_reg[16];
uint32_t rseq_gp_reg[128];
uint32_t rseq_0_reg[32];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t aseq_gp_reg[128];
uint32_t aseq_0_reg[32];
uint32_t aseq_1_reg[16];
uint32_t aseq_2_reg[16];
uint32_t cmd_dma_reg[16];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[128];
uint32_t fpm_hdw_reg[224];
uint32_t fb_hdw_reg[208];
uint32_t code_ram[0x2000];
uint32_t ext_mem[1];
};
struct qla83xx_fw_dump {
uint32_t host_status;
uint32_t host_risc_reg[48];
uint32_t pcie_regs[4];
uint32_t host_reg[32];
uint32_t shadow_reg[11];
uint32_t risc_io_reg;
uint16_t mailbox_reg[32];
uint32_t xseq_gp_reg[256];
uint32_t xseq_0_reg[48];
uint32_t xseq_1_reg[16];
uint32_t xseq_2_reg[16];
uint32_t rseq_gp_reg[256];
uint32_t rseq_0_reg[32];
uint32_t rseq_1_reg[16];
uint32_t rseq_2_reg[16];
uint32_t rseq_3_reg[16];
uint32_t aseq_gp_reg[256];
uint32_t aseq_0_reg[32];
uint32_t aseq_1_reg[16];
uint32_t aseq_2_reg[16];
uint32_t aseq_3_reg[16];
uint32_t cmd_dma_reg[64];
uint32_t req0_dma_reg[15];
uint32_t resp0_dma_reg[15];
uint32_t req1_dma_reg[15];
uint32_t xmt0_dma_reg[32];
uint32_t xmt1_dma_reg[32];
uint32_t xmt2_dma_reg[32];
uint32_t xmt3_dma_reg[32];
uint32_t xmt4_dma_reg[32];
uint32_t xmt_data_dma_reg[16];
uint32_t rcvt0_data_dma_reg[32];
uint32_t rcvt1_data_dma_reg[32];
uint32_t risc_gp_reg[128];
uint32_t lmc_reg[128];
uint32_t fpm_hdw_reg[256];
uint32_t rq0_array_reg[256];
uint32_t rq1_array_reg[256];
uint32_t rp0_array_reg[256];
uint32_t rp1_array_reg[256];
uint32_t queue_control_reg[16];
uint32_t fb_hdw_reg[432];
uint32_t at0_array_reg[128];
uint32_t code_ram[0x2400];
uint32_t ext_mem[1];
};
#define EFT_NUM_BUFFERS 4
#define EFT_BYTES_PER_BUFFER 0x4000
#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
@@ -266,8 +232,31 @@ struct qla2xxx_fce_chain {
uint32_t eregs[8];
};
struct qla2xxx_mq_chain {
uint32_t type;
uint32_t chain_size;
uint32_t count;
uint32_t qregs[4 * QLA_MQ_SIZE];
};
struct qla2xxx_mqueue_header {
uint32_t queue;
#define TYPE_REQUEST_QUEUE 0x1
#define TYPE_RESPONSE_QUEUE 0x2
uint32_t number;
uint32_t size;
};
struct qla2xxx_mqueue_chain {
uint32_t type;
uint32_t chain_size;
};
#define DUMP_CHAIN_VARIANT 0x80000000
#define DUMP_CHAIN_FCE 0x7FFFFAF0
#define DUMP_CHAIN_MQ 0x7FFFFAF1
#define DUMP_CHAIN_QUEUE 0x7FFFFAF2
#define DUMP_CHAIN_LAST 0x80000000
struct qla2xxx_fw_dump {
@@ -300,5 +289,62 @@ struct qla2xxx_fw_dump {
struct qla2300_fw_dump isp23;
struct qla24xx_fw_dump isp24;
struct qla25xx_fw_dump isp25;
struct qla81xx_fw_dump isp81;
struct qla83xx_fw_dump isp83;
} isp;
};
#define QL_MSGHDR "qla2xxx"
#define QL_DBG_DEFAULT1_MASK 0x1e400000
#define ql_log_fatal 0 /* display fatal errors */
#define ql_log_warn 1 /* display critical errors */
#define ql_log_info 2 /* display all recovered errors */
#define ql_log_all 3 /* This value is only used by ql_errlev.
* No messages will use this value.
* This should be always highest value
* as compared to other log levels.
*/
extern int ql_errlev;
void __attribute__((format (printf, 4, 5)))
ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
/* Debug Levels */
/* The 0x40000000 is the max value any debug level can have
* as ql2xextended_error_logging is of type signed int
*/
#define ql_dbg_init 0x40000000 /* Init Debug */
#define ql_dbg_mbx 0x20000000 /* MBX Debug */
#define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
#define ql_dbg_io 0x08000000 /* IO Tracing Debug */
#define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
#define ql_dbg_async 0x02000000 /* Async events Debug */
#define ql_dbg_timer 0x01000000 /* Timer Debug */
#define ql_dbg_user 0x00800000 /* User Space Interations Debug */
#define ql_dbg_taskm 0x00400000 /* Task Management Debug */
#define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
#define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
#define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
#define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
#define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
#define ql_dbg_misc 0x00010000 /* For dumping everything that is not
* not covered by upper categories
*/
#define ql_dbg_verbose 0x00008000 /* More verbosity for each level
* This is to be used with other levels where
* more verbosity is required. It might not
* be applicable to all the levels.
*/
#define ql_dbg_tgt 0x00004000 /* Target mode */
#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
qla2x00t/qla_def.h
+836 -467
View File
File diff suppressed because it is too large Load Diff
qla2x00t/qla_devtbl.h
+1 -1
View File
@@ -72,7 +72,7 @@ static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
"QLA2462", "Sun PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x141 */
"QLE2460", "Sun PCI-Express to 2Gb FC, Single Channel", /* 0x142 */
"QLE2462", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x143 */
"QEM2462" "Server I/O Module 4Gb FC, Dual Channel", /* 0x144 */
"QEM2462", "Server I/O Module 4Gb FC, Dual Channel", /* 0x144 */
"QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */
"QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */
"QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */
qla2x00t/qla_dfs.c
+26 -20
View File
@@ -1,6 +1,6 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
@@ -15,10 +15,11 @@ static atomic_t qla2x00_dfs_root_count;
static int
qla2x00_dfs_fce_show(struct seq_file *s, void *unused)
{
scsi_qla_host_t *ha = s->private;
scsi_qla_host_t *vha = s->private;
uint32_t cnt;
uint32_t *fce;
uint64_t fce_start;
struct qla_hw_data *ha = vha->hw;
mutex_lock(&ha->fce_mutex);
@@ -51,7 +52,8 @@ qla2x00_dfs_fce_show(struct seq_file *s, void *unused)
static int
qla2x00_dfs_fce_open(struct inode *inode, struct file *file)
{
scsi_qla_host_t *ha = inode->i_private;
scsi_qla_host_t *vha = inode->i_private;
struct qla_hw_data *ha = vha->hw;
int rval;
if (!ha->flags.fce_enabled)
@@ -60,22 +62,23 @@ qla2x00_dfs_fce_open(struct inode *inode, struct file *file)
mutex_lock(&ha->fce_mutex);
/* Pause tracing to flush FCE buffers. */
rval = qla2x00_disable_fce_trace(ha, &ha->fce_wr, &ha->fce_rd);
rval = qla2x00_disable_fce_trace(vha, &ha->fce_wr, &ha->fce_rd);
if (rval)
qla_printk(KERN_WARNING, ha,
ql_dbg(ql_dbg_user, vha, 0x705c,
"DebugFS: Unable to disable FCE (%d).\n", rval);
ha->flags.fce_enabled = 0;
mutex_unlock(&ha->fce_mutex);
out:
return single_open(file, qla2x00_dfs_fce_show, ha);
return single_open(file, qla2x00_dfs_fce_show, vha);
}
static int
qla2x00_dfs_fce_release(struct inode *inode, struct file *file)
{
scsi_qla_host_t *ha = inode->i_private;
scsi_qla_host_t *vha = inode->i_private;
struct qla_hw_data *ha = vha->hw;
int rval;
if (ha->flags.fce_enabled)
@@ -86,10 +89,10 @@ qla2x00_dfs_fce_release(struct inode *inode, struct file *file)
/* Re-enable FCE tracing. */
ha->flags.fce_enabled = 1;
memset(ha->fce, 0, fce_calc_size(ha->fce_bufs));
rval = qla2x00_enable_fce_trace(ha, ha->fce_dma, ha->fce_bufs,
rval = qla2x00_enable_fce_trace(vha, ha->fce_dma, ha->fce_bufs,
ha->fce_mb, &ha->fce_bufs);
if (rval) {
qla_printk(KERN_WARNING, ha,
ql_dbg(ql_dbg_user, vha, 0x700d,
"DebugFS: Unable to reinitialize FCE (%d).\n", rval);
ha->flags.fce_enabled = 0;
}
@@ -107,9 +110,11 @@ static const struct file_operations dfs_fce_ops = {
};
int
qla2x00_dfs_setup(scsi_qla_host_t *ha)
qla2x00_dfs_setup(scsi_qla_host_t *vha)
{
if (!IS_QLA25XX(ha))
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
goto out;
if (!ha->fce)
goto out;
@@ -120,8 +125,8 @@ qla2x00_dfs_setup(scsi_qla_host_t *ha)
atomic_set(&qla2x00_dfs_root_count, 0);
qla2x00_dfs_root = debugfs_create_dir(QLA2XXX_DRIVER_NAME, NULL);
if (!qla2x00_dfs_root) {
qla_printk(KERN_NOTICE, ha,
"DebugFS: Unable to create root directory.\n");
ql_log(ql_log_warn, vha, 0x00f7,
"Unable to create debugfs root directory.\n");
goto out;
}
@@ -130,21 +135,21 @@ create_dir:
goto create_nodes;
mutex_init(&ha->fce_mutex);
ha->dfs_dir = debugfs_create_dir(ha->host_str, qla2x00_dfs_root);
ha->dfs_dir = debugfs_create_dir(vha->host_str, qla2x00_dfs_root);
if (!ha->dfs_dir) {
qla_printk(KERN_NOTICE, ha,
"DebugFS: Unable to create ha directory.\n");
ql_log(ql_log_warn, vha, 0x00f8,
"Unable to create debugfs ha directory.\n");
goto out;
}
atomic_inc(&qla2x00_dfs_root_count);
create_nodes:
ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, ha,
ha->dfs_fce = debugfs_create_file("fce", S_IRUSR, ha->dfs_dir, vha,
&dfs_fce_ops);
if (!ha->dfs_fce) {
qla_printk(KERN_NOTICE, ha,
"DebugFS: Unable to fce node.\n");
ql_log(ql_log_warn, vha, 0x00f9,
"Unable to create debugfs fce node.\n");
goto out;
}
out:
@@ -152,8 +157,9 @@ out:
}
int
qla2x00_dfs_remove(scsi_qla_host_t *ha)
qla2x00_dfs_remove(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
if (ha->dfs_fce) {
debugfs_remove(ha->dfs_fce);
ha->dfs_fce = NULL;
qla2x00t/qla_fw.h
+587 -21
View File
@@ -1,6 +1,6 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
@@ -26,6 +26,7 @@
#define PDO_FORCE_ADISC BIT_1
#define PDO_FORCE_PLOGI BIT_0
#ifdef CONFIG_SCSI_QLA2XXX_TARGET
struct qla_port23_data {
uint8_t port_name[WWN_SIZE];
uint16_t loop_id;
@@ -36,6 +37,7 @@ struct qla_port24_data {
uint16_t loop_id;
uint16_t reserved;
};
#endif /* CONFIG_SCSI_QLA2XXX_TARGET */
#define PORT_DATABASE_24XX_SIZE 64
struct port_database_24xx {
@@ -309,7 +311,9 @@ struct init_cb_24xx {
uint32_t response_q_address[2];
uint32_t prio_request_q_address[2];
uint8_t reserved_2[8];
uint16_t msix;
uint16_t msix_atio;
uint8_t reserved_2[4];
uint16_t atio_q_inpointer;
uint16_t atio_q_length;
@@ -382,8 +386,9 @@ struct init_cb_24xx {
* BIT 17-31 = Reserved
*/
uint32_t firmware_options_3;
uint8_t reserved_3[24];
uint16_t qos;
uint16_t rid;
uint8_t reserved_3[20];
};
/*
@@ -408,6 +413,7 @@ struct cmd_type_6 {
struct scsi_lun lun; /* FCP LUN (BE). */
uint16_t control_flags; /* Control flags. */
#define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define CF_DATA_SEG_DESCR_ENABLE BIT_2
#define CF_READ_DATA BIT_1
#define CF_WRITE_DATA BIT_0
@@ -423,8 +429,7 @@ struct cmd_type_6 {
uint8_t vp_index;
uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
uint16_t fcp_data_dseg_len; /* Data segment length. */
uint16_t reserved_1; /* MUST be set to 0. */
uint32_t fcp_data_dseg_len; /* Data segment length. */
};
#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
@@ -474,6 +479,43 @@ struct cmd_type_7 {
uint32_t dseg_0_len; /* Data segment 0 length. */
};
#define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
* (T10-DIF) */
struct cmd_type_crc_2 {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint16_t nport_handle; /* N_PORT handle. */
uint16_t timeout; /* Command timeout. */
uint16_t dseg_count; /* Data segment count. */
uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
struct scsi_lun lun; /* FCP LUN (BE). */
uint16_t control_flags; /* Control flags. */
uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
uint32_t byte_count; /* Total byte count. */
uint8_t port_id[3]; /* PortID of destination port. */
uint8_t vp_index;
uint32_t crc_context_address[2]; /* Data segment address. */
uint16_t crc_context_len; /* Data segment length. */
uint16_t reserved_1; /* MUST be set to 0. */
};
/*
* ISP queue - status entry structure definition.
*/
@@ -504,10 +546,22 @@ struct sts_entry_24xx {
uint32_t sense_len; /* FCP SENSE length. */
uint32_t rsp_data_len; /* FCP response data length. */
uint8_t data[28]; /* FCP response/sense information. */
/*
* If DIF Error is set in comp_status, these additional fields are
* defined:
*
* !!! NOTE: Firmware sends expected/actual DIF data in big endian
* format; but all of the "data" field gets swab32-d in the beginning
* of qla2x00_status_entry().
*
* &data[10] : uint8_t report_runt_bg[2]; - computed guard
* &data[12] : uint8_t actual_dif[8]; - DIF Data received
* &data[20] : uint8_t expected_dif[8]; - DIF Data computed
*/
};
/*
* Status entry completion status
*/
@@ -635,6 +689,39 @@ struct els_entry_24xx {
uint32_t rx_len; /* Data segment 1 length. */
};
struct els_sts_entry_24xx {
uint8_t entry_type; /* Entry type. */
uint8_t entry_count; /* Entry count. */
uint8_t sys_define; /* System Defined. */
uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */
uint16_t comp_status;
uint16_t nport_handle; /* N_PORT handle. */
uint16_t reserved_1;
uint8_t vp_index;
uint8_t sof_type;
uint32_t rx_xchg_address; /* Receive exchange address. */
uint16_t reserved_2;
uint8_t opcode;
uint8_t reserved_3;
uint8_t port_id[3];
uint8_t reserved_4;
uint16_t reserved_5;
uint16_t control_flags; /* Control flags. */
uint32_t total_byte_count;
uint32_t error_subcode_1;
uint32_t error_subcode_2;
};
/*
* ISP queue - Mailbox Command entry structure definition.
*/
@@ -764,7 +851,8 @@ struct abort_entry_24xx {
uint32_t handle_to_abort; /* System handle to abort. */
uint8_t reserved_1[32];
uint16_t req_que_no;
uint8_t reserved_1[30];
uint8_t port_id[3]; /* PortID of destination port. */
uint8_t vp_index;
@@ -799,14 +887,25 @@ struct device_reg_24xx {
#define FA_RISC_CODE_ADDR 0x20000
#define FA_RISC_CODE_SEGMENTS 2
#define FA_FLASH_DESCR_ADDR_24 0x11000
#define FA_FLASH_LAYOUT_ADDR_24 0x11400
#define FA_NPIV_CONF0_ADDR_24 0x16000
#define FA_NPIV_CONF1_ADDR_24 0x17000
#define FA_FW_AREA_ADDR 0x40000
#define FA_VPD_NVRAM_ADDR 0x48000
#define FA_FEATURE_ADDR 0x4C000
#define FA_FLASH_DESCR_ADDR 0x50000
#define FA_FLASH_LAYOUT_ADDR 0x50400
#define FA_HW_EVENT0_ADDR 0x54000
#define FA_HW_EVENT1_ADDR 0x54200
#define FA_HW_EVENT1_ADDR 0x54400
#define FA_HW_EVENT_SIZE 0x200
#define FA_HW_EVENT_ENTRY_SIZE 4
#define FA_NPIV_CONF0_ADDR 0x5C000
#define FA_NPIV_CONF1_ADDR 0x5D000
#define FA_FCP_PRIO0_ADDR 0x10000
#define FA_FCP_PRIO1_ADDR 0x12000
/*
* Flash Error Log Event Codes.
*/
@@ -816,10 +915,6 @@ struct device_reg_24xx {
#define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
#define HW_EVENT_FLASH_FW_ERR 0xF024
#define FA_BOOT_LOG_ADDR 0x58000
#define FA_FW_DUMP0_ADDR 0x60000
#define FA_FW_DUMP1_ADDR 0x70000
uint32_t flash_data; /* Flash/NVRAM BIOS data. */
uint32_t ctrl_status; /* Control/Status. */
@@ -880,7 +975,6 @@ struct device_reg_24xx {
/* HCCR statuses. */
#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
/* HCCR commands. */
/* NOOP. */
#define HCCRX_NOOP 0x00000000
@@ -993,12 +1087,12 @@ struct device_reg_24xx {
#define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
#define MAX_MULTI_ID_FABRIC 256 /* ... */
#define for_each_mapped_vp_idx(_ha, _idx) \
for (_idx = find_next_bit((_ha)->vp_idx_map, \
(_ha)->max_npiv_vports + 1, 1); \
_idx <= (_ha)->max_npiv_vports; \
_idx = find_next_bit((_ha)->vp_idx_map, \
(_ha)->max_npiv_vports + 1, _idx + 1)) \
#define for_each_mapped_vp_idx(_vha, _idx) \
for (_idx = find_next_bit((_vha)->hw->vp_idx_map, \
(_vha)->hw->max_npiv_vports + 1, 1); \
_idx <= (_vha)->hw->max_npiv_vports; \
_idx = find_next_bit((_vha)->hw->vp_idx_map, \
(_vha)->hw->max_npiv_vports + 1, _idx + 1)) \
struct mid_conf_entry_24xx {
uint16_t reserved_1;
@@ -1129,7 +1223,7 @@ struct vp_config_entry_24xx {
uint16_t id;
uint16_t reserved_4;
uint16_t hopct;
uint8_t reserved_5;
uint8_t reserved_5[2];
};
#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
@@ -1213,6 +1307,72 @@ struct qla_fdt_layout {
uint8_t unused2[65];
};
/* Flash Layout Table ********************************************************/
struct qla_flt_location {
uint8_t sig[4];
uint16_t start_lo;
uint16_t start_hi;
uint8_t version;
uint8_t unused[5];
uint16_t checksum;
};
struct qla_flt_header {
uint16_t version;
uint16_t length;
uint16_t checksum;
uint16_t unused;
};
#define FLT_REG_FW 0x01
#define FLT_REG_BOOT_CODE 0x07
#define FLT_REG_VPD_0 0x14
#define FLT_REG_NVRAM_0 0x15
#define FLT_REG_VPD_1 0x16
#define FLT_REG_NVRAM_1 0x17
#define FLT_REG_FDT 0x1a
#define FLT_REG_FLT 0x1c
#define FLT_REG_HW_EVENT_0 0x1d
#define FLT_REG_HW_EVENT_1 0x1f
#define FLT_REG_NPIV_CONF_0 0x29
#define FLT_REG_NPIV_CONF_1 0x2a
#define FLT_REG_GOLD_FW 0x2f
#define FLT_REG_FCP_PRIO_0 0x87
#define FLT_REG_FCP_PRIO_1 0x88
#define FLT_REG_FCOE_FW 0xA4
#define FLT_REG_FCOE_VPD_0 0xA9
#define FLT_REG_FCOE_NVRAM_0 0xAA
#define FLT_REG_FCOE_VPD_1 0xAB
#define FLT_REG_FCOE_NVRAM_1 0xAC
struct qla_flt_region {
uint32_t code;
uint32_t size;
uint32_t start;
uint32_t end;
};
/* Flash NPIV Configuration Table ********************************************/
struct qla_npiv_header {
uint8_t sig[2];
uint16_t version;
uint16_t entries;
uint16_t unused[4];
uint16_t checksum;
};
struct qla_npiv_entry {
uint16_t flags;
uint16_t vf_id;
uint8_t q_qos;
uint8_t f_qos;
uint16_t unused1;
uint8_t port_name[WWN_SIZE];
uint8_t node_name[WWN_SIZE];
};
/* 84XX Support **************************************************************/
#define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
@@ -1335,4 +1495,410 @@ struct access_chip_rsp_84xx {
uint32_t reserved[12];
};
/* 81XX Support **************************************************************/
#define MBA_DCBX_START 0x8016
#define MBA_DCBX_COMPLETE 0x8030
#define MBA_FCF_CONF_ERR 0x8031
#define MBA_DCBX_PARAM_UPDATE 0x8032
#define MBA_IDC_COMPLETE 0x8100
#define MBA_IDC_NOTIFY 0x8101
#define MBA_IDC_TIME_EXT 0x8102
#define MBC_IDC_ACK 0x101
#define MBC_RESTART_MPI_FW 0x3d
#define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
#define MBC_GET_XGMAC_STATS 0x7a
#define MBC_GET_DCBX_PARAMS 0x51
/*
* ISP83xx mailbox commands
*/
#define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
/* Flash access control option field bit definitions */
#define FAC_OPT_FORCE_SEMAPHORE BIT_15
#define FAC_OPT_REQUESTOR_ID BIT_14
#define FAC_OPT_CMD_SUBCODE 0xff
/* Flash access control command subcodes */
#define FAC_OPT_CMD_WRITE_PROTECT 0x00
#define FAC_OPT_CMD_WRITE_ENABLE 0x01
#define FAC_OPT_CMD_ERASE_SECTOR 0x02
#define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
#define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
#define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
struct nvram_81xx {
/* NVRAM header. */
uint8_t id[4];
uint16_t nvram_version;
uint16_t reserved_0;
/* Firmware Initialization Control Block. */
uint16_t version;
uint16_t reserved_1;
uint16_t frame_payload_size;
uint16_t execution_throttle;
uint16_t exchange_count;
uint16_t reserved_2;
uint8_t port_name[WWN_SIZE];
uint8_t node_name[WWN_SIZE];
uint16_t login_retry_count;
uint16_t reserved_3;
uint16_t interrupt_delay_timer;
uint16_t login_timeout;
uint32_t firmware_options_1;
uint32_t firmware_options_2;
uint32_t firmware_options_3;
uint16_t reserved_4[4];
/* Offset 64. */
uint8_t enode_mac[6];
uint16_t reserved_5[5];
/* Offset 80. */
uint16_t reserved_6[24];
/* Offset 128. */
uint16_t ex_version;
uint8_t prio_fcf_matching_flags;
uint8_t reserved_6_1[3];
uint16_t pri_fcf_vlan_id;
uint8_t pri_fcf_fabric_name[8];
uint16_t reserved_6_2[7];
uint8_t spma_mac_addr[6];
uint16_t reserved_6_3[14];
/* Offset 192. */
uint16_t reserved_7[32];
/*
* BIT 0 = Enable spinup delay
* BIT 1 = Disable BIOS
* BIT 2 = Enable Memory Map BIOS
* BIT 3 = Enable Selectable Boot
* BIT 4 = Disable RISC code load
* BIT 5 = Disable Serdes
* BIT 6 = Opt boot mode
* BIT 7 = Interrupt enable
*
* BIT 8 = EV Control enable
* BIT 9 = Enable lip reset
* BIT 10 = Enable lip full login
* BIT 11 = Enable target reset
* BIT 12 = Stop firmware
* BIT 13 = Enable nodename option
* BIT 14 = Default WWPN valid
* BIT 15 = Enable alternate WWN
*
* BIT 16 = CLP LUN string
* BIT 17 = CLP Target string
* BIT 18 = CLP BIOS enable string
* BIT 19 = CLP Serdes string
* BIT 20 = CLP WWPN string
* BIT 21 = CLP WWNN string
* BIT 22 =
* BIT 23 =
* BIT 24 = Keep WWPN
* BIT 25 = Temp WWPN
* BIT 26-31 =
*/
uint32_t host_p;
uint8_t alternate_port_name[WWN_SIZE];
uint8_t alternate_node_name[WWN_SIZE];
uint8_t boot_port_name[WWN_SIZE];
uint16_t boot_lun_number;
uint16_t reserved_8;
uint8_t alt1_boot_port_name[WWN_SIZE];
uint16_t alt1_boot_lun_number;
uint16_t reserved_9;
uint8_t alt2_boot_port_name[WWN_SIZE];
uint16_t alt2_boot_lun_number;
uint16_t reserved_10;
uint8_t alt3_boot_port_name[WWN_SIZE];
uint16_t alt3_boot_lun_number;
uint16_t reserved_11;
/*
* BIT 0 = Selective Login
* BIT 1 = Alt-Boot Enable
* BIT 2 = Reserved
* BIT 3 = Boot Order List
* BIT 4 = Reserved
* BIT 5 = Selective LUN
* BIT 6 = Reserved
* BIT 7-31 =
*/
uint32_t efi_parameters;
uint8_t reset_delay;
uint8_t reserved_12;
uint16_t reserved_13;
uint16_t boot_id_number;
uint16_t reserved_14;
uint16_t max_luns_per_target;
uint16_t reserved_15;
uint16_t port_down_retry_count;
uint16_t link_down_timeout;
/* FCode parameters. */
uint16_t fcode_parameter;
uint16_t reserved_16[3];
/* Offset 352. */
uint8_t reserved_17[4];
uint16_t reserved_18[5];
uint8_t reserved_19[2];
uint16_t reserved_20[8];
/* Offset 384. */
uint8_t reserved_21[16];
uint16_t reserved_22[3];
/*
* BIT 0 = Extended BB credits for LR
* BIT 1 = Virtual Fabric Enable
* BIT 2 = Enhanced Features Unused
* BIT 3-7 = Enhanced Features Reserved
*/
/* Enhanced Features */
uint8_t enhanced_features;
uint8_t reserved_23;
uint16_t reserved_24[4];
/* Offset 416. */
uint16_t reserved_25[32];
/* Offset 480. */
uint8_t model_name[16];
/* Offset 496. */
uint16_t feature_mask_l;
uint16_t feature_mask_h;
uint16_t reserved_26[2];
uint16_t subsystem_vendor_id;
uint16_t subsystem_device_id;
uint32_t checksum;
};
/*
* ISP Initialization Control Block.
* Little endian except where noted.
*/
#define ICB_VERSION 1
struct init_cb_81xx {
uint16_t version;
uint16_t reserved_1;
uint16_t frame_payload_size;
uint16_t execution_throttle;
uint16_t exchange_count;
uint16_t reserved_2;
uint8_t port_name[WWN_SIZE]; /* Big endian. */
uint8_t node_name[WWN_SIZE]; /* Big endian. */
uint16_t response_q_inpointer;
uint16_t request_q_outpointer;
uint16_t login_retry_count;
uint16_t prio_request_q_outpointer;
uint16_t response_q_length;
uint16_t request_q_length;
uint16_t reserved_3;
uint16_t prio_request_q_length;
uint32_t request_q_address[2];
uint32_t response_q_address[2];
uint32_t prio_request_q_address[2];
uint8_t reserved_4[8];
uint16_t atio_q_inpointer;
uint16_t atio_q_length;
uint32_t atio_q_address[2];
uint16_t interrupt_delay_timer; /* 100us increments. */
uint16_t login_timeout;
/*
* BIT 0-3 = Reserved
* BIT 4 = Enable Target Mode
* BIT 5 = Disable Initiator Mode
* BIT 6 = Reserved
* BIT 7 = Reserved
*
* BIT 8-13 = Reserved
* BIT 14 = Node Name Option
* BIT 15-31 = Reserved
*/
uint32_t firmware_options_1;
/*
* BIT 0 = Operation Mode bit 0
* BIT 1 = Operation Mode bit 1
* BIT 2 = Operation Mode bit 2
* BIT 3 = Operation Mode bit 3
* BIT 4-7 = Reserved
*
* BIT 8 = Enable Class 2
* BIT 9 = Enable ACK0
* BIT 10 = Reserved
* BIT 11 = Enable FC-SP Security
* BIT 12 = FC Tape Enable
* BIT 13 = Reserved
* BIT 14 = Enable Target PRLI Control
* BIT 15-31 = Reserved
*/
uint32_t firmware_options_2;
/*
* BIT 0-3 = Reserved
* BIT 4 = FCP RSP Payload bit 0
* BIT 5 = FCP RSP Payload bit 1
* BIT 6 = Enable Receive Out-of-Order data frame handling
* BIT 7 = Reserved
*
* BIT 8 = Reserved
* BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
* BIT 10-16 = Reserved
* BIT 17 = Enable multiple FCFs
* BIT 18-20 = MAC addressing mode
* BIT 21-25 = Ethernet data rate
* BIT 26 = Enable ethernet header rx IOCB for ATIO q
* BIT 27 = Enable ethernet header rx IOCB for response q
* BIT 28 = SPMA selection bit 0
* BIT 28 = SPMA selection bit 1
* BIT 30-31 = Reserved
*/
uint32_t firmware_options_3;
uint8_t reserved_5[8];
uint8_t enode_mac[6];
uint8_t reserved_6[10];
};
struct mid_init_cb_81xx {
struct init_cb_81xx init_cb;
uint16_t count;
uint16_t options;
struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
};
struct ex_init_cb_81xx {
uint16_t ex_version;
uint8_t prio_fcf_matching_flags;
uint8_t reserved_1[3];
uint16_t pri_fcf_vlan_id;
uint8_t pri_fcf_fabric_name[8];
uint16_t reserved_2[7];
uint8_t spma_mac_addr[6];
uint16_t reserved_3[14];
};
#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
/* FCP priority config defines *************************************/
/* operations */
#define QLFC_FCP_PRIO_DISABLE 0x0
#define QLFC_FCP_PRIO_ENABLE 0x1
#define QLFC_FCP_PRIO_GET_CONFIG 0x2
#define QLFC_FCP_PRIO_SET_CONFIG 0x3
struct qla_fcp_prio_entry {
uint16_t flags; /* Describes parameter(s) in FCP */
/* priority entry that are valid */
#define FCP_PRIO_ENTRY_VALID 0x1
#define FCP_PRIO_ENTRY_TAG_VALID 0x2
#define FCP_PRIO_ENTRY_SPID_VALID 0x4
#define FCP_PRIO_ENTRY_DPID_VALID 0x8
#define FCP_PRIO_ENTRY_LUNB_VALID 0x10
#define FCP_PRIO_ENTRY_LUNE_VALID 0x20
#define FCP_PRIO_ENTRY_SWWN_VALID 0x40
#define FCP_PRIO_ENTRY_DWWN_VALID 0x80
uint8_t tag; /* Priority value */
uint8_t reserved; /* Reserved for future use */
uint32_t src_pid; /* Src port id. high order byte */
/* unused; -1 (wild card) */
uint32_t dst_pid; /* Src port id. high order byte */
/* unused; -1 (wild card) */
uint16_t lun_beg; /* 1st lun num of lun range. */
/* -1 (wild card) */
uint16_t lun_end; /* 2nd lun num of lun range. */
/* -1 (wild card) */
uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
};
struct qla_fcp_prio_cfg {
uint8_t signature[4]; /* "HQOS" signature of config data */
uint16_t version; /* 1: Initial version */
uint16_t length; /* config data size in num bytes */
uint16_t checksum; /* config data bytes checksum */
uint16_t num_entries; /* Number of entries */
uint16_t size_of_entry; /* Size of each entry in num bytes */
uint8_t attributes; /* enable/disable, persistence */
#define FCP_PRIO_ATTR_DISABLE 0x0
#define FCP_PRIO_ATTR_ENABLE 0x1
#define FCP_PRIO_ATTR_PERSIST 0x2
uint8_t reserved; /* Reserved for future use */
#define FCP_PRIO_CFG_HDR_SIZE 0x10
struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */
#define FCP_PRIO_CFG_ENTRY_SIZE 0x20
};
#define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
/* 25XX Support ****************************************************/
#define FA_FCP_PRIO0_ADDR_25 0x3C000
#define FA_FCP_PRIO1_ADDR_25 0x3E000
/* 81XX Flash locations -- occupies second 2MB region. */
#define FA_BOOT_CODE_ADDR_81 0x80000
#define FA_RISC_CODE_ADDR_81 0xA0000
#define FA_FW_AREA_ADDR_81 0xC0000
#define FA_VPD_NVRAM_ADDR_81 0xD0000
#define FA_VPD0_ADDR_81 0xD0000
#define FA_VPD1_ADDR_81 0xD0400
#define FA_NVRAM0_ADDR_81 0xD0080
#define FA_NVRAM1_ADDR_81 0xD0180
#define FA_FEATURE_ADDR_81 0xD4000
#define FA_FLASH_DESCR_ADDR_81 0xD8000
#define FA_FLASH_LAYOUT_ADDR_81 0xD8400
#define FA_HW_EVENT0_ADDR_81 0xDC000
#define FA_HW_EVENT1_ADDR_81 0xDC400
#define FA_NPIV_CONF0_ADDR_81 0xD1000
#define FA_NPIV_CONF1_ADDR_81 0xD2000
/* 83XX Flash locations -- occupies second 8MB region. */
#define FA_FLASH_LAYOUT_ADDR_83 0xFC400
#endif
qla2x00t/qla_gbl.h
+286 -43
View File
@@ -1,6 +1,6 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
@@ -28,19 +28,25 @@ extern void qla2x00_reset_adapter(struct scsi_qla_host *);
extern void qla24xx_reset_adapter(struct scsi_qla_host *);
extern int qla2x00_nvram_config(struct scsi_qla_host *);
extern int qla24xx_nvram_config(struct scsi_qla_host *);
extern int qla81xx_nvram_config(struct scsi_qla_host *);
extern void qla2x00_update_fw_options(struct scsi_qla_host *);
extern void qla24xx_update_fw_options(scsi_qla_host_t *);
extern void qla81xx_update_fw_options(scsi_qla_host_t *);
extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *);
extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *);
extern int qla81xx_load_risc(scsi_qla_host_t *, uint32_t *);
extern int qla2x00_perform_loop_resync(scsi_qla_host_t *);
extern int qla2x00_loop_resync(scsi_qla_host_t *);
extern int qla2x00_find_new_loop_id(scsi_qla_host_t *, fc_port_t *);
extern int qla2x00_fabric_login(scsi_qla_host_t *, fc_port_t *, uint16_t *);
extern int qla2x00_local_device_login(scsi_qla_host_t *, fc_port_t *);
extern void qla2x00_update_fcports(scsi_qla_host_t *);
extern int qla2x00_abort_isp(scsi_qla_host_t *);
extern void qla2x00_abort_isp_cleanup(scsi_qla_host_t *);
extern void qla82xx_quiescent_state_cleanup(scsi_qla_host_t *);
extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *);
@@ -51,13 +57,29 @@ extern void qla2x00_enable_tgt_mode(scsi_qla_host_t *ha);
extern void qla2x00_disable_tgt_mode(scsi_qla_host_t *ha);
extern int qla2x00_issue_marker(scsi_qla_host_t *ha, int ha_locked);
extern int qla2x00_get_thermal_temp(scsi_qla_host_t *, uint16_t *, uint16_t *);
extern void qla84xx_put_chip(struct scsi_qla_host *);
extern int qla2x00_configure_loop(scsi_qla_host_t *);
extern int qla2x00_configure_local_loop(scsi_qla_host_t *);
extern int qla2x00_configure_fabric(scsi_qla_host_t *);
extern int qla2x00_async_login(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_async_logout(struct scsi_qla_host *, fc_port_t *);
extern int qla2x00_async_adisc(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_async_tm_cmd(fc_port_t *, uint32_t, uint32_t, uint32_t);
extern void qla2x00_async_login_done(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern void qla2x00_async_logout_done(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern void qla2x00_async_adisc_done(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern void *qla2x00_alloc_iocbs(struct scsi_qla_host *, srb_t *);
extern fc_port_t *
qla2x00_alloc_fcport(scsi_qla_host_t *, gfp_t );
/*
* Global Data in qla_os.c source file.
*/
@@ -70,41 +92,75 @@ extern int ql2xloginretrycount;
extern int ql2xfdmienable;
extern int ql2xallocfwdump;
extern int ql2xextended_error_logging;
extern int ql2xqfullrampup;
extern int ql2xiidmaenable;
extern int ql2xmaxqueues;
extern int ql2xmultique_tag;
extern int ql2xfwloadbin;
extern int ql2xetsenable;
extern int ql2xshiftctondsd;
extern int ql2xdbwr;
extern int ql2xdontresethba;
extern unsigned int ql2xmaxlun;
extern int ql2xasynctmfenable;
extern int ql2xenabledif;
extern int ql2xenablehba_err_chk;
extern int ql2xtargetreset;
extern int ql2xgffidenable;
extern int ql2xmdcapmask;
extern int ql2xmdenable;
extern int num_hosts;
extern int qla2x00_loop_reset(scsi_qla_host_t *);
extern void qla2x00_abort_all_cmds(scsi_qla_host_t *, int);
extern int qla2x00_post_aen_work(struct scsi_qla_host *, enum
fc_host_event_code, u32);
extern int qla2x00_post_hwe_work(struct scsi_qla_host *, uint16_t , uint16_t,
uint16_t, uint16_t);
extern int qla2x00_post_idc_ack_work(struct scsi_qla_host *, uint16_t *);
extern int qla2x00_post_async_login_work(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_post_async_login_done_work(struct scsi_qla_host *,
fc_port_t *, uint16_t *);
extern int qla2x00_post_async_logout_work(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_post_async_logout_done_work(struct scsi_qla_host *,
fc_port_t *, uint16_t *);
extern int qla2x00_post_async_adisc_work(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_post_async_adisc_done_work(struct scsi_qla_host *,
fc_port_t *, uint16_t *);
extern int qla2x00_post_uevent_work(struct scsi_qla_host *, u32);
extern void qla2x00_abort_fcport_cmds(fc_port_t *);
extern int qla81xx_restart_mpi_firmware(scsi_qla_host_t *);
extern struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *,
struct qla_hw_data *);
extern void qla2x00_free_host(struct scsi_qla_host *);
extern void qla2x00_relogin(struct scsi_qla_host *);
extern void qla2x00_do_work(struct scsi_qla_host *);
extern void qla2x00_free_fcports(struct scsi_qla_host *);
/*
* Global Functions in qla_mid.c source file.
*/
extern struct scsi_host_template qla24xx_driver_template;
extern struct scsi_host_template qla2xxx_driver_template;
extern struct scsi_transport_template *qla2xxx_transport_vport_template;
extern void qla2x00_timer(scsi_qla_host_t *);
extern void qla2x00_start_timer(scsi_qla_host_t *, void *, unsigned long);
extern void qla24xx_deallocate_vp_id(scsi_qla_host_t *);
extern int qla24xx_disable_vp (scsi_qla_host_t *);
extern int qla24xx_enable_vp (scsi_qla_host_t *);
extern int qla24xx_init_vp(scsi_qla_host_t *);
extern int qla24xx_disable_vp(scsi_qla_host_t *);
extern int qla24xx_enable_vp(scsi_qla_host_t *);
extern int qla24xx_control_vp(scsi_qla_host_t *, int );
extern int qla24xx_modify_vp_config(scsi_qla_host_t *);
extern int qla2x00_send_change_request(scsi_qla_host_t *, uint16_t, uint16_t);
extern void qla2x00_vp_stop_timer(scsi_qla_host_t *);
extern int qla24xx_configure_vhba (scsi_qla_host_t *);
extern int qla24xx_configure_vhba(scsi_qla_host_t *);
extern void qla24xx_report_id_acquisition(scsi_qla_host_t *,
struct vp_rpt_id_entry_24xx *);
extern void qla2x00_do_dpc_all_vps(scsi_qla_host_t *);
extern int qla24xx_vport_create_req_sanity_check(struct fc_vport *);
extern scsi_qla_host_t * qla24xx_create_vhost(struct fc_vport *);
extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *);
extern scsi_qla_host_t *qla24xx_create_vhost(struct fc_vport *);
extern void qla2x00_sp_free_dma(void *, void *);
extern char *qla2x00_get_fw_version_str(struct scsi_qla_host *, char *);
extern void qla2x00_mark_device_lost(scsi_qla_host_t *, fc_port_t *, int, int);
@@ -113,25 +169,33 @@ extern void qla2x00_mark_all_devices_lost(scsi_qla_host_t *, int);
extern struct fw_blob *qla2x00_request_firmware(scsi_qla_host_t *);
extern int qla2x00_wait_for_hba_online(scsi_qla_host_t *);
extern int qla2x00_wait_for_chip_reset(scsi_qla_host_t *);
extern int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *);
extern void qla2xxx_wake_dpc(scsi_qla_host_t *);
extern void qla2x00_alert_all_vps(scsi_qla_host_t *, uint16_t *);
extern void qla2x00_async_event(scsi_qla_host_t *, uint16_t *);
extern void qla2x00_vp_abort_isp(scsi_qla_host_t *);
extern void qla2xxx_wake_dpc(struct scsi_qla_host *);
extern void qla2x00_alert_all_vps(struct rsp_que *, uint16_t *);
extern void qla2x00_async_event(scsi_qla_host_t *, struct rsp_que *,
uint16_t *);
extern int qla2x00_vp_abort_isp(scsi_qla_host_t *);
/*
* Global Function Prototypes in qla_iocb.c source file.
*/
extern void qla2x00_isp_cmd(scsi_qla_host_t *);
extern void qla2x00_start_iocbs(struct scsi_qla_host *, struct req_que *);
extern uint16_t qla2x00_calc_iocbs_32(uint16_t);
extern uint16_t qla2x00_calc_iocbs_64(uint16_t);
extern void qla2x00_build_scsi_iocbs_32(srb_t *, cmd_entry_t *, uint16_t);
extern void qla2x00_build_scsi_iocbs_64(srb_t *, cmd_entry_t *, uint16_t);
extern int qla2x00_start_scsi(srb_t *sp);
extern int qla24xx_start_scsi(srb_t *sp);
int qla2x00_marker(scsi_qla_host_t *, uint16_t, uint16_t, uint8_t);
int __qla2x00_marker(scsi_qla_host_t *, uint16_t, uint16_t, uint8_t);
extern int qla2x00_marker(struct scsi_qla_host *, struct req_que *, struct rsp_que *,
uint16_t, uint16_t, uint8_t);
extern int __qla2x00_marker(struct scsi_qla_host *, struct req_que *,
struct rsp_que *, uint16_t, uint16_t, uint8_t);
extern int qla2x00_start_sp(srb_t *);
extern uint16_t qla24xx_calc_iocbs(scsi_qla_host_t *, uint16_t);
extern void qla24xx_build_scsi_iocbs(srb_t *, struct cmd_type_7 *, uint16_t);
extern int qla24xx_dif_start_scsi(srb_t *);
/*
* Global Function Prototypes in qla_mbx.c source file.
@@ -145,9 +209,8 @@ qla2x00_dump_ram(scsi_qla_host_t *, dma_addr_t, uint32_t, uint32_t);
extern int
qla2x00_execute_fw(scsi_qla_host_t *, uint32_t);
extern void
qla2x00_get_fw_version(scsi_qla_host_t *, uint16_t *,
uint16_t *, uint16_t *, uint16_t *, uint32_t *);
extern int
qla2x00_get_fw_version(scsi_qla_host_t *);
extern int
qla2x00_get_fw_options(scsi_qla_host_t *, uint16_t *);
@@ -165,13 +228,13 @@ extern int
qla2x00_issue_iocb(scsi_qla_host_t *, void *, dma_addr_t, size_t);
extern int
qla2x00_abort_command(scsi_qla_host_t *, srb_t *);
qla2x00_abort_command(srb_t *);
extern int
qla2x00_abort_target(struct fc_port *, unsigned int);
qla2x00_abort_target(struct fc_port *, unsigned int, int);
extern int
qla2x00_lun_reset(struct fc_port *, unsigned int);
qla2x00_lun_reset(struct fc_port *, unsigned int, int);
extern int
qla2x00_get_adapter_id(scsi_qla_host_t *, uint16_t *, uint8_t *, uint8_t *,
@@ -183,9 +246,11 @@ qla2x00_get_retry_cnt(scsi_qla_host_t *, uint8_t *, uint8_t *, uint16_t *);
extern int
qla2x00_init_firmware(scsi_qla_host_t *, uint16_t);
#ifdef CONFIG_SCSI_QLA2XXX_TARGET
extern int
qla2x00_get_node_name_list(scsi_qla_host_t *ha,
qla2x00_get_node_name_list(scsi_qla_host_t *ha, bool include_initiators,
void **out_data, int *out_len);
#endif
extern int
qla2x00_get_port_database(scsi_qla_host_t *, fc_port_t *, uint8_t);
@@ -227,7 +292,7 @@ qla2x00_get_id_list(scsi_qla_host_t *, void *, dma_addr_t, uint16_t *);
extern int
qla2x00_get_resource_cnts(scsi_qla_host_t *, uint16_t *, uint16_t *,
uint16_t *, uint16_t *, uint16_t *);
uint16_t *, uint16_t *, uint16_t *, uint16_t *);
extern int
qla2x00_get_fcal_position_map(scsi_qla_host_t *ha, char *pos_map);
@@ -240,10 +305,14 @@ extern int
qla24xx_get_isp_stats(scsi_qla_host_t *, struct link_statistics *,
dma_addr_t);
extern int qla24xx_abort_command(scsi_qla_host_t *, srb_t *);
extern int qla24xx_abort_target(struct fc_port *, unsigned int);
extern int qla24xx_lun_reset(struct fc_port *, unsigned int);
extern int qla24xx_abort_command(srb_t *);
extern int
qla24xx_abort_target(struct fc_port *, unsigned int, int);
extern int
qla24xx_lun_reset(struct fc_port *, unsigned int, int);
extern int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *, unsigned int,
unsigned int, enum nexus_wait_type);
extern int
qla2x00_system_error(scsi_qla_host_t *);
@@ -266,25 +335,73 @@ extern int
qla2x00_disable_fce_trace(scsi_qla_host_t *, uint64_t *, uint64_t *);
extern int
qla2x00_read_sfp(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t, uint16_t);
qla2x00_read_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,
uint16_t, uint16_t, uint16_t, uint16_t);
extern int
qla2x00_write_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,
uint16_t, uint16_t, uint16_t, uint16_t);
extern int
qla2x00_set_idma_speed(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t *);
extern int qla84xx_verify_chip(struct scsi_qla_host *, uint16_t *);
extern int qla81xx_idc_ack(scsi_qla_host_t *, uint16_t *);
extern int
qla81xx_fac_get_sector_size(scsi_qla_host_t *, uint32_t *);
extern int
qla81xx_fac_do_write_enable(scsi_qla_host_t *, int);
extern int
qla81xx_fac_erase_sector(scsi_qla_host_t *, uint32_t, uint32_t);
extern int
qla2x00_get_xgmac_stats(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t *);
extern int
qla2x00_get_dcbx_params(scsi_qla_host_t *, dma_addr_t, uint16_t);
extern int
qla2x00_read_ram_word(scsi_qla_host_t *, uint32_t, uint32_t *);
extern int
qla2x00_write_ram_word(scsi_qla_host_t *, uint32_t, uint32_t);
extern int
qla81xx_write_mpi_register(scsi_qla_host_t *, uint16_t *);
extern int qla2x00_get_data_rate(scsi_qla_host_t *);
extern int qla24xx_set_fcp_prio(scsi_qla_host_t *, uint16_t, uint16_t,
uint16_t *);
extern int
qla81xx_get_port_config(scsi_qla_host_t *, uint16_t *);
extern int
qla81xx_set_port_config(scsi_qla_host_t *, uint16_t *);
extern int
qla2x00_port_logout(scsi_qla_host_t *, struct fc_port *);
/*
* Global Function Prototypes in qla_isr.c source file.
*/
extern irqreturn_t qla2100_intr_handler(int, void *);
extern irqreturn_t qla2300_intr_handler(int, void *);
extern irqreturn_t qla24xx_intr_handler(int, void *);
extern void qla2x00_process_response_queue(struct scsi_qla_host *);
extern void qla24xx_process_response_queue(struct scsi_qla_host *);
extern int qla2x00_request_irqs(scsi_qla_host_t *);
extern void qla2x00_process_response_queue(struct rsp_que *);
extern void
qla24xx_process_response_queue(struct scsi_qla_host *, struct rsp_que *);
#ifdef CONFIG_SCSI_QLA2XXX_TARGET
extern void qla24xx_process_atio_queue(struct scsi_qla_host *ha);
#endif
extern int qla2x00_request_irqs(struct qla_hw_data *, struct rsp_que *);
extern void qla2x00_free_irqs(scsi_qla_host_t *);
extern int qla2x00_get_data_rate(scsi_qla_host_t *);
extern char* qla2x00_get_link_speed_str(struct qla_hw_data *);
/*
* Global Function Prototypes in qla_sup.c source file.
*/
@@ -310,6 +427,11 @@ extern void qla2x00_beacon_blink(struct scsi_qla_host *);
extern int qla24xx_beacon_on(struct scsi_qla_host *);
extern int qla24xx_beacon_off(struct scsi_qla_host *);
extern void qla24xx_beacon_blink(struct scsi_qla_host *);
extern void qla83xx_beacon_blink(struct scsi_qla_host *);
extern int qla82xx_beacon_on(struct scsi_qla_host *);
extern int qla82xx_beacon_off(struct scsi_qla_host *);
extern int qla83xx_write_remote_reg(scsi_qla_host_t *ha, uint32_t reg,
uint32_t data);
extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
uint32_t, uint32_t);
@@ -325,12 +447,12 @@ extern uint8_t *qla25xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
extern int qla2x00_get_flash_version(scsi_qla_host_t *, void *);
extern int qla24xx_get_flash_version(scsi_qla_host_t *, void *);
extern int qla2xxx_hw_event_log(scsi_qla_host_t *, uint16_t , uint16_t,
uint16_t, uint16_t);
extern void qla2xxx_get_flash_info(scsi_qla_host_t *);
extern int qla2xxx_get_flash_info(scsi_qla_host_t *);
extern int qla2xxx_get_vpd_field(scsi_qla_host_t *, char *, char *, size_t);
extern void qla2xxx_flash_npiv_conf(scsi_qla_host_t *);
extern int qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp);
extern int qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *);
/*
* Global Function Prototypes in qla_dbg.c source file.
@@ -339,8 +461,14 @@ extern void qla2100_fw_dump(scsi_qla_host_t *, int);
extern void qla2300_fw_dump(scsi_qla_host_t *, int);
extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
extern void qla25xx_fw_dump(scsi_qla_host_t *, int);
extern void qla81xx_fw_dump(scsi_qla_host_t *, int);
extern void qla2x00_dump_regs(scsi_qla_host_t *);
extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
extern void qla2x00_dump_buffer_zipped(uint8_t *, uint32_t);
extern void qla2xxx_dump_post_process(scsi_qla_host_t *, int);
extern void ql_dump_regs(uint32_t, scsi_qla_host_t *, int32_t);
extern void ql_dump_buffer(uint32_t, scsi_qla_host_t *, int32_t,
uint8_t *, uint32_t);
/*
* Global Function Prototypes in qla_gs.c source file.
@@ -351,6 +479,7 @@ extern int qla2x00_ga_nxt(scsi_qla_host_t *, fc_port_t *);
extern int qla2x00_gid_pt(scsi_qla_host_t *, sw_info_t *);
extern int qla2x00_gpn_id(scsi_qla_host_t *, sw_info_t *);
extern int qla2x00_gnn_id(scsi_qla_host_t *, sw_info_t *);
extern void qla2x00_gff_id(scsi_qla_host_t *, sw_info_t *);
extern int qla2x00_rft_id(scsi_qla_host_t *);
extern int qla2x00_rff_id(scsi_qla_host_t *);
extern int qla2x00_rnn_id(scsi_qla_host_t *);
@@ -361,7 +490,6 @@ extern int qla2x00_fdmi_register(scsi_qla_host_t *);
extern int qla2x00_gfpn_id(scsi_qla_host_t *, sw_info_t *);
extern int qla2x00_gpsc(scsi_qla_host_t *, sw_info_t *);
extern void qla2x00_get_sym_node_name(scsi_qla_host_t *, uint8_t *);
extern int qla2x00_mgmt_svr_login(scsi_qla_host_t *);
/*
* Global Function Prototypes in qla_attr.c source file.
@@ -376,10 +504,125 @@ extern void qla2x00_free_sysfs_attr(scsi_qla_host_t *);
extern void qla2x00_init_host_attr(scsi_qla_host_t *);
extern void qla2x00_alloc_sysfs_attr(scsi_qla_host_t *);
extern void qla2x00_free_sysfs_attr(scsi_qla_host_t *);
extern int qla2x00_loopback_test(scsi_qla_host_t *, struct msg_echo_lb *, uint16_t *);
extern int qla2x00_echo_test(scsi_qla_host_t *,
struct msg_echo_lb *, uint16_t *);
extern int qla24xx_update_all_fcp_prio(scsi_qla_host_t *);
extern int qla24xx_fcp_prio_cfg_valid(scsi_qla_host_t *,
struct qla_fcp_prio_cfg *, uint8_t);
/*
* Global Function Prototypes in qla_dfs.c source file.
*/
extern int qla2x00_dfs_setup(scsi_qla_host_t *);
extern int qla2x00_dfs_remove(scsi_qla_host_t *);
/* Globa function prototypes for multi-q */
extern int qla25xx_request_irq(struct rsp_que *);
extern int qla25xx_init_req_que(struct scsi_qla_host *, struct req_que *);
extern int qla25xx_init_rsp_que(struct scsi_qla_host *, struct rsp_que *);
extern int qla25xx_create_req_que(struct qla_hw_data *, uint16_t, uint8_t,
uint16_t, int, uint8_t);
extern int qla25xx_create_rsp_que(struct qla_hw_data *, uint16_t, uint8_t,
uint16_t, int);
extern void qla2x00_init_response_q_entries(struct rsp_que *);
extern int qla25xx_delete_req_que(struct scsi_qla_host *, struct req_que *);
extern int qla25xx_delete_queues(struct scsi_qla_host *);
extern uint16_t qla24xx_rd_req_reg(struct qla_hw_data *, uint16_t);
extern uint16_t qla25xx_rd_req_reg(struct qla_hw_data *, uint16_t);
extern void qla24xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t);
extern void qla25xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t);
extern void qla25xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
/* qla82xx related functions */
/* PCI related functions */
extern int qla82xx_pci_config(struct scsi_qla_host *);
extern char *qla82xx_pci_info_str(struct scsi_qla_host *, char *, int);
extern int qla82xx_iospace_config(struct qla_hw_data *);
/* Initialization related functions */
extern void qla82xx_reset_chip(struct scsi_qla_host *);
extern void qla82xx_config_rings(struct scsi_qla_host *);
extern void qla82xx_watchdog(scsi_qla_host_t *);
extern int qla82xx_start_firmware(scsi_qla_host_t *);
extern void qla2x00_set_model_info(scsi_qla_host_t *, uint8_t *,
size_t, char *);
/* Firmware and flash related functions */
extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *);
extern uint8_t *qla82xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
uint32_t, uint32_t);
extern int qla82xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
uint32_t, uint32_t);
/* Mailbox related functions */
extern int qla82xx_abort_isp(scsi_qla_host_t *);
extern int qla82xx_restart_isp(scsi_qla_host_t *);
extern int qla82xx_mbx_intr_enable(scsi_qla_host_t *);
extern int qla82xx_mbx_intr_disable(scsi_qla_host_t *);
/* IOCB related functions */
extern int qla82xx_start_scsi(srb_t *);
extern void qla82xx_start_iocbs(scsi_qla_host_t *);
extern void qla2x00_sp_free(void *, void *);
extern void qla2x00_sp_timeout(unsigned long);
extern void qla2x00_bsg_job_done(void *, void *, int);
extern void qla2x00_bsg_sp_free(void *, void *);
/* Interrupt related */
extern irqreturn_t qla82xx_intr_handler(int, void *);
extern irqreturn_t qla82xx_msix_default(int, void *);
extern irqreturn_t qla82xx_msix_rsp_q(int, void *);
extern void qla82xx_enable_intrs(struct qla_hw_data *);
extern void qla82xx_disable_intrs(struct qla_hw_data *);
extern void qla82xx_poll(int, void *);
extern void qla82xx_init_flags(struct qla_hw_data *);
/* ISP 8021 hardware related */
extern void qla82xx_set_drv_active(scsi_qla_host_t *);
extern int qla82xx_wr_32(struct qla_hw_data *, ulong, u32);
extern int qla82xx_rd_32(struct qla_hw_data *, ulong);
/* ISP 8021 IDC */
extern void qla82xx_clear_drv_active(struct qla_hw_data *);
extern uint32_t qla82xx_wait_for_state_change(scsi_qla_host_t *, uint32_t);
extern int qla82xx_idc_lock(struct qla_hw_data *);
extern void qla82xx_idc_unlock(struct qla_hw_data *);
extern int qla82xx_device_state_handler(scsi_qla_host_t *);
extern void qla82xx_clear_qsnt_ready(scsi_qla_host_t *);
/* Reset related */
extern int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *);
extern int qla82xx_check_md_needed(scsi_qla_host_t *);
extern void qla82xx_chip_reset_cleanup(scsi_qla_host_t *);
extern int qla81xx_set_led_config(scsi_qla_host_t *, uint16_t *);
extern int qla81xx_get_led_config(scsi_qla_host_t *, uint16_t *);
extern char *qdev_state(uint32_t);
extern int qla82xx_mbx_beacon_ctl(scsi_qla_host_t *, int);
extern void qla82xx_clear_pending_mbx(scsi_qla_host_t *);
/* BSG related functions */
extern int qla24xx_bsg_request(struct fc_bsg_job *);
extern int qla24xx_bsg_timeout(struct fc_bsg_job *);
extern int qla84xx_reset_chip(scsi_qla_host_t *, uint16_t);
extern int qla2x00_issue_iocb_timeout(scsi_qla_host_t *, void *,
dma_addr_t, size_t, uint32_t);
extern int qla2x00_get_idma_speed(scsi_qla_host_t *, uint16_t,
uint16_t *, uint16_t *);
/* 83xx related functions */
extern void qla83xx_fw_dump(scsi_qla_host_t *, int);
extern int qla83xx_configure_vfs(scsi_qla_host_t *);
/* Minidump related functions */
extern int qla82xx_md_get_template_size(scsi_qla_host_t *);
extern int qla82xx_md_get_template(scsi_qla_host_t *);
extern int qla82xx_md_alloc(scsi_qla_host_t *);
extern void qla82xx_md_free(scsi_qla_host_t *);
extern int qla82xx_md_collect(scsi_qla_host_t *);
extern void qla82xx_md_prep(scsi_qla_host_t *);
extern void qla82xx_set_reset_owner(scsi_qla_host_t *);
#endif /* _QLA_GBL_H */
qla2x00t/qla_gs.c
+511 -392
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qla2x00t/qla_init.c
+2786 -1259
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qla2x00t/qla_inline.h
+131 -13
View File
@@ -1,6 +1,6 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
@@ -32,17 +32,20 @@ qla2x00_debounce_register(volatile uint16_t __iomem *addr)
}
static inline void
qla2x00_poll(scsi_qla_host_t *ha)
qla2x00_poll(struct rsp_que *rsp)
{
unsigned long flags;
struct qla_hw_data *ha = rsp->hw;
#ifdef CONFIG_PREEMPT_RT_FULL
local_irq_save_nort(flags);
#else
local_irq_save(flags);
#endif
ha->isp_ops->intr_handler(0, ha);
if (IS_QLA82XX(ha))
qla82xx_poll(0, rsp);
else
ha->isp_ops->intr_handler(0, rsp);
#ifdef CONFIG_PREEMPT_RT_FULL
local_irq_restore_nort(flags);
@@ -51,12 +54,6 @@ qla2x00_poll(scsi_qla_host_t *ha)
#endif
}
static __inline__ scsi_qla_host_t *
to_qla_parent(scsi_qla_host_t *ha)
{
return ha->parent ? ha->parent : ha;
}
static inline uint8_t *
host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
{
@@ -71,11 +68,132 @@ host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
}
static inline int
qla2x00_is_reserved_id(scsi_qla_host_t *ha, uint16_t loop_id)
qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
{
struct qla_hw_data *ha = vha->hw;
if (IS_FWI2_CAPABLE(ha))
return (loop_id > NPH_LAST_HANDLE);
return ((loop_id > ha->last_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
return ((loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST);
};
}
static inline void
qla2x00_clean_dsd_pool(struct qla_hw_data *ha, srb_t *sp)
{
struct dsd_dma *dsd_ptr, *tdsd_ptr;
struct crc_context *ctx;
ctx = (struct crc_context *)GET_CMD_CTX_SP(sp);
/* clean up allocated prev pool */
list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
&ctx->dsd_list, list) {
dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
dsd_ptr->dsd_list_dma);
list_del(&dsd_ptr->list);
kfree(dsd_ptr);
}
INIT_LIST_HEAD(&ctx->dsd_list);
}
static inline void
qla2x00_set_fcport_state(fc_port_t *fcport, int state)
{
int old_state;
old_state = atomic_read(&fcport->state);
atomic_set(&fcport->state, state);
/* Don't print state transitions during initial allocation of fcport */
if (old_state && old_state != state) {
ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
"FCPort state transitioned from %s to %s - "
"portid=%02x%02x%02x.\n",
port_state_str[old_state], port_state_str[state],
fcport->d_id.b.domain, fcport->d_id.b.area,
fcport->d_id.b.al_pa);
}
}
static inline int
qla2x00_hba_err_chk_enabled(srb_t *sp)
{
/*
* Uncomment when corresponding SCSI changes are done.
*
if (!sp->cmd->prot_chk)
return 0;
*
*/
switch (scsi_get_prot_op(GET_CMD_SP(sp))) {
case SCSI_PROT_READ_STRIP:
case SCSI_PROT_WRITE_INSERT:
if (ql2xenablehba_err_chk >= 1)
return 1;
break;
case SCSI_PROT_READ_PASS:
case SCSI_PROT_WRITE_PASS:
if (ql2xenablehba_err_chk >= 2)
return 1;
break;
case SCSI_PROT_READ_INSERT:
case SCSI_PROT_WRITE_STRIP:
return 1;
}
return 0;
}
static inline srb_t *
qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag)
{
srb_t *sp = NULL;
struct qla_hw_data *ha = vha->hw;
uint8_t bail;
QLA_VHA_MARK_BUSY(vha, bail);
if (unlikely(bail))
return NULL;
sp = mempool_alloc(ha->srb_mempool, flag);
if (!sp)
goto done;
memset(sp, 0, sizeof(*sp));
sp->fcport = fcport;
sp->iocbs = 1;
done:
if (!sp)
QLA_VHA_MARK_NOT_BUSY(vha);
return sp;
}
static inline void
qla2x00_init_timer(srb_t *sp, unsigned long tmo)
{
init_timer(&sp->u.iocb_cmd.timer);
sp->u.iocb_cmd.timer.expires = jiffies + tmo * HZ;
sp->u.iocb_cmd.timer.data = (unsigned long)sp;
sp->u.iocb_cmd.timer.function = qla2x00_sp_timeout;
add_timer(&sp->u.iocb_cmd.timer);
sp->free = qla2x00_sp_free;
}
static inline int
qla2x00_reset_active(scsi_qla_host_t *vha)
{
scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev);
/* Test appropriate base-vha and vha flags. */
return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) ||
test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
}
static inline int
qla2x00_gid_list_size(struct qla_hw_data *ha)
{
return (sizeof(struct gid_list_info) * ha->max_fibre_devices);
}
qla2x00t/qla_iocb.c
+2135 -227
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qla2x00t/qla_isr.c
+1672 -1038
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qla2x00t/qla_mbx.c
+2487 -666
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qla2x00t/qla_mid.c
+597 -172
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qla2x00t/qla_nx.c
+4463
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qla2x00t/qla_nx.h
+1194
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qla2x00t/qla_os.c
+2850 -1290
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qla2x00t/qla_settings.h
+1 -1
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@@ -1,6 +1,6 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
qla2x00t/qla_sup.c
+1087 -463
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File diff suppressed because it is too large Load Diff
qla2x00t/qla_version.h
+4 -4
View File
@@ -1,15 +1,15 @@
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2008 QLogic Corporation
* Copyright (c) 2003-2011 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
/*
* Driver version
*/
#define QLA2XXX_VERSION "8.02.01-k4-tgt"
#define QLA2XXX_VERSION "8.04.00.05.2.2-SCST.03-k-p"
#define QLA_DRIVER_MAJOR_VER 8
#define QLA_DRIVER_MINOR_VER 2
#define QLA_DRIVER_PATCH_VER 1
#define QLA_DRIVER_MINOR_VER 4
#define QLA_DRIVER_PATCH_VER 0
#define QLA_DRIVER_BETA_VER 0