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Merge branch 'svn-trunk'

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This commit is contained in:
Bart Van Assche
2019-04-13 18:36:31 -07:00
parent 53c2d01e81 338d9d7611
commit a72c9010e2
26 changed files with 2803 additions and 1693 deletions
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qla2x00t-32gbit/qla_attr.c
+214 -102
View File
@@ -29,24 +29,27 @@ qla2x00_sysfs_read_fw_dump(struct file *filp, struct kobject *kobj,
if (!(ha->fw_dump_reading || ha->mctp_dump_reading))
return 0;
mutex_lock(&ha->optrom_mutex);
if (IS_P3P_TYPE(ha)) {
if (off < ha->md_template_size) {
rval = memory_read_from_buffer(buf, count,
&off, ha->md_tmplt_hdr, ha->md_template_size);
return rval;
} else {
off -= ha->md_template_size;
rval = memory_read_from_buffer(buf, count,
&off, ha->md_dump, ha->md_dump_size);
}
off -= ha->md_template_size;
rval = memory_read_from_buffer(buf, count,
&off, ha->md_dump, ha->md_dump_size);
return rval;
} else if (ha->mctp_dumped && ha->mctp_dump_reading)
return memory_read_from_buffer(buf, count, &off, ha->mctp_dump,
} else if (ha->mctp_dumped && ha->mctp_dump_reading) {
rval = memory_read_from_buffer(buf, count, &off, ha->mctp_dump,
MCTP_DUMP_SIZE);
else if (ha->fw_dump_reading)
return memory_read_from_buffer(buf, count, &off, ha->fw_dump,
} else if (ha->fw_dump_reading) {
rval = memory_read_from_buffer(buf, count, &off, ha->fw_dump,
ha->fw_dump_len);
else
return 0;
} else {
rval = 0;
}
mutex_unlock(&ha->optrom_mutex);
return rval;
}
static ssize_t
@@ -154,6 +157,8 @@ qla2x00_sysfs_read_nvram(struct file *filp, struct kobject *kobj,
struct scsi_qla_host *vha = shost_priv(dev_to_shost(container_of(kobj,
struct device, kobj)));
struct qla_hw_data *ha = vha->hw;
uint32_t faddr;
struct active_regions active_regions = { };
if (!capable(CAP_SYS_ADMIN))
return 0;
@@ -164,11 +169,21 @@ qla2x00_sysfs_read_nvram(struct file *filp, struct kobject *kobj,
return -EAGAIN;
}
if (IS_NOCACHE_VPD_TYPE(ha))
ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
ha->nvram_size);
if (!IS_NOCACHE_VPD_TYPE(ha)) {
mutex_unlock(&ha->optrom_mutex);
goto skip;
}
faddr = ha->flt_region_nvram;
if (IS_QLA28XX(ha)) {
if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
faddr = ha->flt_region_nvram_sec;
}
ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size);
mutex_unlock(&ha->optrom_mutex);
skip:
return memory_read_from_buffer(buf, count, &off, ha->nvram,
ha->nvram_size);
}
@@ -223,9 +238,9 @@ qla2x00_sysfs_write_nvram(struct file *filp, struct kobject *kobj,
}
/* Write NVRAM. */
ha->isp_ops->write_nvram(vha, (uint8_t *)buf, ha->nvram_base, count);
ha->isp_ops->read_nvram(vha, (uint8_t *)ha->nvram, ha->nvram_base,
count);
ha->isp_ops->write_nvram(vha, buf, ha->nvram_base, count);
ha->isp_ops->read_nvram(vha, ha->nvram, ha->nvram_base,
count);
mutex_unlock(&ha->optrom_mutex);
ql_dbg(ql_dbg_user, vha, 0x7060,
@@ -364,7 +379,7 @@ qla2x00_sysfs_write_optrom_ctl(struct file *filp, struct kobject *kobj,
}
ha->optrom_region_start = start;
ha->optrom_region_size = start + size;
ha->optrom_region_size = size;
ha->optrom_state = QLA_SREADING;
ha->optrom_buffer = vmalloc(ha->optrom_region_size);
@@ -418,6 +433,10 @@ qla2x00_sysfs_write_optrom_ctl(struct file *filp, struct kobject *kobj,
* 0x000000 -> 0x07ffff -- Boot code.
* 0x080000 -> 0x0fffff -- Firmware.
* 0x120000 -> 0x12ffff -- VPD and HBA parameters.
*
* > ISP25xx type boards:
*
* None -- should go through BSG.
*/
valid = 0;
if (ha->optrom_size == OPTROM_SIZE_2300 && start == 0)
@@ -425,9 +444,7 @@ qla2x00_sysfs_write_optrom_ctl(struct file *filp, struct kobject *kobj,
else if (start == (ha->flt_region_boot * 4) ||
start == (ha->flt_region_fw * 4))
valid = 1;
else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)
|| IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)
|| IS_QLA27XX(ha))
else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
valid = 1;
if (!valid) {
ql_log(ql_log_warn, vha, 0x7065,
@@ -437,7 +454,7 @@ qla2x00_sysfs_write_optrom_ctl(struct file *filp, struct kobject *kobj,
}
ha->optrom_region_start = start;
ha->optrom_region_size = start + size;
ha->optrom_region_size = size;
ha->optrom_state = QLA_SWRITING;
ha->optrom_buffer = vmalloc(ha->optrom_region_size);
@@ -504,6 +521,7 @@ qla2x00_sysfs_read_vpd(struct file *filp, struct kobject *kobj,
struct device, kobj)));
struct qla_hw_data *ha = vha->hw;
uint32_t faddr;
struct active_regions active_regions = { };
if (unlikely(pci_channel_offline(ha->pdev)))
return -EAGAIN;
@@ -511,22 +529,33 @@ qla2x00_sysfs_read_vpd(struct file *filp, struct kobject *kobj,
if (!capable(CAP_SYS_ADMIN))
return -EINVAL;
if (IS_NOCACHE_VPD_TYPE(ha)) {
faddr = ha->flt_region_vpd << 2;
if (IS_NOCACHE_VPD_TYPE(ha))
goto skip;
if (IS_QLA27XX(ha) &&
qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
faddr = ha->flt_region_vpd << 2;
if (IS_QLA28XX(ha)) {
qla28xx_get_aux_images(vha, &active_regions);
if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
faddr = ha->flt_region_vpd_sec << 2;
mutex_lock(&ha->optrom_mutex);
if (qla2x00_chip_is_down(vha)) {
mutex_unlock(&ha->optrom_mutex);
return -EAGAIN;
}
ha->isp_ops->read_optrom(vha, ha->vpd, faddr,
ha->vpd_size);
mutex_unlock(&ha->optrom_mutex);
ql_dbg(ql_dbg_init, vha, 0x7070,
"Loading %s nvram image.\n",
active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
"primary" : "secondary");
}
mutex_lock(&ha->optrom_mutex);
if (qla2x00_chip_is_down(vha)) {
mutex_unlock(&ha->optrom_mutex);
return -EAGAIN;
}
ha->isp_ops->read_optrom(vha, ha->vpd, faddr, ha->vpd_size);
mutex_unlock(&ha->optrom_mutex);
ha->isp_ops->read_optrom(vha, ha->vpd, faddr, ha->vpd_size);
skip:
return memory_read_from_buffer(buf, count, &off, ha->vpd, ha->vpd_size);
}
@@ -563,8 +592,8 @@ qla2x00_sysfs_write_vpd(struct file *filp, struct kobject *kobj,
}
/* Write NVRAM. */
ha->isp_ops->write_nvram(vha, (uint8_t *)buf, ha->vpd_base, count);
ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, ha->vpd_base, count);
ha->isp_ops->write_nvram(vha, buf, ha->vpd_base, count);
ha->isp_ops->read_nvram(vha, ha->vpd, ha->vpd_base, count);
/* Update flash version information for 4Gb & above. */
if (!IS_FWI2_CAPABLE(ha)) {
@@ -682,7 +711,7 @@ qla2x00_sysfs_write_reset(struct file *filp, struct kobject *kobj,
ql_log(ql_log_info, vha, 0x706f,
"Issuing MPI reset.\n");
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
uint32_t idc_control;
qla83xx_idc_lock(vha, 0);
@@ -934,7 +963,7 @@ static struct bin_attribute sysfs_dcbx_tlv_attr = {
static struct sysfs_entry {
char *name;
struct bin_attribute *attr;
int is4GBp_only;
int type;
} bin_file_entries[] = {
{ "fw_dump", &sysfs_fw_dump_attr, },
{ "nvram", &sysfs_nvram_attr, },
@@ -957,11 +986,11 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *vha)
int ret;
for (iter = bin_file_entries; iter->name; iter++) {
if (iter->is4GBp_only && !IS_FWI2_CAPABLE(vha->hw))
if (iter->type && !IS_FWI2_CAPABLE(vha->hw))
continue;
if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw))
if (iter->type == 2 && !IS_QLA25XX(vha->hw))
continue;
if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
if (iter->type == 3 && !(IS_CNA_CAPABLE(vha->hw)))
continue;
ret = sysfs_create_bin_file(&host->shost_gendev.kobj,
@@ -985,13 +1014,14 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *vha, bool stop_beacon)
struct qla_hw_data *ha = vha->hw;
for (iter = bin_file_entries; iter->name; iter++) {
if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha))
if (iter->type && !IS_FWI2_CAPABLE(ha))
continue;
if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha))
if (iter->type == 2 && !IS_QLA25XX(ha))
continue;
if (iter->is4GBp_only == 3 && !(IS_CNA_CAPABLE(vha->hw)))
if (iter->type == 3 && !(IS_CNA_CAPABLE(ha)))
continue;
if (iter->is4GBp_only == 0x27 && !IS_QLA27XX(vha->hw))
if (iter->type == 0x27 &&
(!IS_QLA27XX(ha) || !IS_QLA28XX(ha)))
continue;
sysfs_remove_bin_file(&host->shost_gendev.kobj,
@@ -1336,7 +1366,8 @@ qla2x00_optrom_gold_fw_version_show(struct device *dev,
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%d)\n",
@@ -1358,23 +1389,39 @@ qla24xx_84xx_fw_version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int rval = QLA_SUCCESS;
uint16_t status[2] = {0, 0};
uint16_t status[2] = { 0 };
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA84XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
if (ha->cs84xx->op_fw_version == 0)
if (!ha->cs84xx->op_fw_version) {
rval = qla84xx_verify_chip(vha, status);
if ((rval == QLA_SUCCESS) && (status[0] == 0))
return scnprintf(buf, PAGE_SIZE, "%u\n",
(uint32_t)ha->cs84xx->op_fw_version);
if (!rval && !status[0])
return scnprintf(buf, PAGE_SIZE, "%u\n",
(uint32_t)ha->cs84xx->op_fw_version);
}
return scnprintf(buf, PAGE_SIZE, "\n");
}
static ssize_t
qla2x00_serdes_version_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%d.%02d.%02d\n",
ha->serdes_version[0], ha->serdes_version[1],
ha->serdes_version[2]);
}
static ssize_t
qla2x00_mpi_version_show(struct device *dev, struct device_attribute *attr,
char *buf)
@@ -1383,7 +1430,7 @@ qla2x00_mpi_version_show(struct device *dev, struct device_attribute *attr,
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA81XX(ha) && !IS_QLA8031(ha) && !IS_QLA8044(ha) &&
!IS_QLA27XX(ha))
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%d.%02d.%02d (%x)\n",
@@ -1596,7 +1643,7 @@ qla2x00_pep_version_show(struct device *dev, struct device_attribute *attr,
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(ha))
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%d.%02d.%02d\n",
@@ -1604,35 +1651,38 @@ qla2x00_pep_version_show(struct device *dev, struct device_attribute *attr,
}
static ssize_t
qla2x00_min_link_speed_show(struct device *dev, struct device_attribute *attr,
char *buf)
qla2x00_min_supported_speed_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(ha))
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%s\n",
ha->min_link_speed == 5 ? "32Gps" :
ha->min_link_speed == 4 ? "16Gps" :
ha->min_link_speed == 3 ? "8Gps" :
ha->min_link_speed == 2 ? "4Gps" :
ha->min_link_speed != 0 ? "unknown" : "");
ha->min_supported_speed == 6 ? "64Gps" :
ha->min_supported_speed == 5 ? "32Gps" :
ha->min_supported_speed == 4 ? "16Gps" :
ha->min_supported_speed == 3 ? "8Gps" :
ha->min_supported_speed == 2 ? "4Gps" :
ha->min_supported_speed != 0 ? "unknown" : "");
}
static ssize_t
qla2x00_max_speed_sup_show(struct device *dev, struct device_attribute *attr,
char *buf)
qla2x00_max_supported_speed_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(ha))
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%s\n",
ha->max_speed_sup ? "32Gps" : "16Gps");
ha->max_supported_speed == 2 ? "64Gps" :
ha->max_supported_speed == 1 ? "32Gps" :
ha->max_supported_speed == 0 ? "16Gps" : "unknown");
}
static ssize_t
@@ -1645,7 +1695,7 @@ qla2x00_port_speed_store(struct device *dev, struct device_attribute *attr,
int mode = QLA_SET_DATA_RATE_LR;
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(vha->hw)) {
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) {
ql_log(ql_log_warn, vha, 0x70d8,
"Speed setting not supported \n");
return -EINVAL;
@@ -2164,6 +2214,32 @@ qla2x00_dif_bundle_statistics_show(struct device *dev,
ha->dif_bundle_dma_allocs, ha->pool.unusable.count);
}
static ssize_t
qla2x00_fw_attr_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return scnprintf(buf, PAGE_SIZE, "\n");
return scnprintf(buf, PAGE_SIZE, "%llx\n",
(uint64_t)ha->fw_attributes_ext[1] << 48 |
(uint64_t)ha->fw_attributes_ext[0] << 32 |
(uint64_t)ha->fw_attributes_h << 16 |
(uint64_t)ha->fw_attributes);
}
static ssize_t
qla2x00_port_no_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
return scnprintf(buf, PAGE_SIZE, "%u\n", vha->hw->port_no);
}
static DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_driver_version_show, NULL);
static DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL);
static DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL);
@@ -2192,6 +2268,7 @@ static DEVICE_ATTR(84xx_fw_version, S_IRUGO, qla24xx_84xx_fw_version_show,
NULL);
static DEVICE_ATTR(total_isp_aborts, S_IRUGO, qla2x00_total_isp_aborts_show,
NULL);
static DEVICE_ATTR(serdes_version, 0444, qla2x00_serdes_version_show, NULL);
static DEVICE_ATTR(mpi_version, S_IRUGO, qla2x00_mpi_version_show, NULL);
static DEVICE_ATTR(phy_version, S_IRUGO, qla2x00_phy_version_show, NULL);
static DEVICE_ATTR(flash_block_size, S_IRUGO, qla2x00_flash_block_size_show,
@@ -2209,8 +2286,10 @@ static DEVICE_ATTR(allow_cna_fw_dump, S_IRUGO | S_IWUSR,
qla2x00_allow_cna_fw_dump_show,
qla2x00_allow_cna_fw_dump_store);
static DEVICE_ATTR(pep_version, S_IRUGO, qla2x00_pep_version_show, NULL);
static DEVICE_ATTR(min_link_speed, S_IRUGO, qla2x00_min_link_speed_show, NULL);
static DEVICE_ATTR(max_speed_sup, S_IRUGO, qla2x00_max_speed_sup_show, NULL);
static DEVICE_ATTR(min_supported_speed, 0444,
qla2x00_min_supported_speed_show, NULL);
static DEVICE_ATTR(max_supported_speed, 0444,
qla2x00_max_supported_speed_show, NULL);
static DEVICE_ATTR(zio_threshold, 0644,
qla_zio_threshold_show,
qla_zio_threshold_store);
@@ -2221,6 +2300,8 @@ static DEVICE_ATTR(dif_bundle_statistics, 0444,
qla2x00_dif_bundle_statistics_show, NULL);
static DEVICE_ATTR(port_speed, 0644, qla2x00_port_speed_show,
qla2x00_port_speed_store);
static DEVICE_ATTR(port_no, 0444, qla2x00_port_no_show, NULL);
static DEVICE_ATTR(fw_attr, 0444, qla2x00_fw_attr_show, NULL);
struct device_attribute *qla2x00_host_attrs[] = {
@@ -2242,6 +2323,7 @@ struct device_attribute *qla2x00_host_attrs[] = {
&dev_attr_optrom_fw_version,
&dev_attr_84xx_fw_version,
&dev_attr_total_isp_aborts,
&dev_attr_serdes_version,
&dev_attr_mpi_version,
&dev_attr_phy_version,
&dev_attr_flash_block_size,
@@ -2256,11 +2338,13 @@ struct device_attribute *qla2x00_host_attrs[] = {
&dev_attr_fw_dump_size,
&dev_attr_allow_cna_fw_dump,
&dev_attr_pep_version,
&dev_attr_min_link_speed,
&dev_attr_max_speed_sup,
&dev_attr_min_supported_speed,
&dev_attr_max_supported_speed,
&dev_attr_zio_threshold,
&dev_attr_dif_bundle_statistics,
&dev_attr_port_speed,
&dev_attr_port_no,
&dev_attr_fw_attr,
NULL, /* reserve for qlini_mode */
NULL, /* reserve for ql2xiniexchg */
NULL, /* reserve for ql2xexchoffld */
@@ -2296,16 +2380,15 @@ qla2x00_get_host_port_id(struct Scsi_Host *shost)
static void
qla2x00_get_host_speed(struct Scsi_Host *shost)
{
struct qla_hw_data *ha = ((struct scsi_qla_host *)
(shost_priv(shost)))->hw;
u32 speed = FC_PORTSPEED_UNKNOWN;
scsi_qla_host_t *vha = shost_priv(shost);
u32 speed;
if (IS_QLAFX00(ha)) {
if (IS_QLAFX00(vha->hw)) {
qlafx00_get_host_speed(shost);
return;
}
switch (ha->link_data_rate) {
switch (vha->hw->link_data_rate) {
case PORT_SPEED_1GB:
speed = FC_PORTSPEED_1GBIT;
break;
@@ -2327,7 +2410,14 @@ qla2x00_get_host_speed(struct Scsi_Host *shost)
case PORT_SPEED_32GB:
speed = FC_PORTSPEED_32GBIT;
break;
case PORT_SPEED_64GB:
speed = FC_PORTSPEED_64GBIT;
break;
default:
speed = FC_PORTSPEED_UNKNOWN;
break;
}
fc_host_speed(shost) = speed;
}
@@ -2335,7 +2425,7 @@ static void
qla2x00_get_host_port_type(struct Scsi_Host *shost)
{
scsi_qla_host_t *vha = shost_priv(shost);
uint32_t port_type = FC_PORTTYPE_UNKNOWN;
uint32_t port_type;
if (vha->vp_idx) {
fc_host_port_type(shost) = FC_PORTTYPE_NPIV;
@@ -2354,7 +2444,11 @@ qla2x00_get_host_port_type(struct Scsi_Host *shost)
case ISP_CFG_F:
port_type = FC_PORTTYPE_NPORT;
break;
default:
port_type = FC_PORTTYPE_UNKNOWN;
break;
}
fc_host_port_type(shost) = port_type;
}
@@ -2416,13 +2510,10 @@ qla2x00_get_starget_port_id(struct scsi_target *starget)
fc_starget_port_id(starget) = port_id;
}
static void
static inline void
qla2x00_set_rport_loss_tmo(struct fc_rport *rport, uint32_t timeout)
{
if (timeout)
rport->dev_loss_tmo = timeout;
else
rport->dev_loss_tmo = 1;
rport->dev_loss_tmo = timeout ? timeout : 1;
}
static void
@@ -2632,8 +2723,9 @@ static void
qla2x00_get_host_fabric_name(struct Scsi_Host *shost)
{
scsi_qla_host_t *vha = shost_priv(shost);
uint8_t node_name[WWN_SIZE] = { 0xFF, 0xFF, 0xFF, 0xFF, \
0xFF, 0xFF, 0xFF, 0xFF};
static const uint8_t node_name[WWN_SIZE] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
};
u64 fabric_name = wwn_to_u64(node_name);
if (vha->device_flags & SWITCH_FOUND)
@@ -2977,7 +3069,7 @@ void
qla2x00_init_host_attr(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
u32 speed = FC_PORTSPEED_UNKNOWN;
u32 speeds = FC_PORTSPEED_UNKNOWN;
fc_host_dev_loss_tmo(vha->host) = ha->port_down_retry_count;
fc_host_node_name(vha->host) = wwn_to_u64(vha->node_name);
@@ -2988,25 +3080,45 @@ qla2x00_init_host_attr(scsi_qla_host_t *vha)
fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count;
if (IS_CNA_CAPABLE(ha))
speed = FC_PORTSPEED_10GBIT;
else if (IS_QLA2031(ha))
speed = FC_PORTSPEED_16GBIT | FC_PORTSPEED_8GBIT |
FC_PORTSPEED_4GBIT;
else if (IS_QLA25XX(ha))
speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT |
FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT;
speeds = FC_PORTSPEED_10GBIT;
else if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) {
if (ha->max_supported_speed == 2) {
if (ha->min_supported_speed <= 6)
speeds |= FC_PORTSPEED_64GBIT;
}
if (ha->max_supported_speed == 2 ||
ha->max_supported_speed == 1) {
if (ha->min_supported_speed <= 5)
speeds |= FC_PORTSPEED_32GBIT;
}
if (ha->max_supported_speed == 2 ||
ha->max_supported_speed == 1 ||
ha->max_supported_speed == 0) {
if (ha->min_supported_speed <= 4)
speeds |= FC_PORTSPEED_16GBIT;
}
if (ha->max_supported_speed == 1 ||
ha->max_supported_speed == 0) {
if (ha->min_supported_speed <= 3)
speeds |= FC_PORTSPEED_8GBIT;
}
if (ha->max_supported_speed == 0) {
if (ha->min_supported_speed <= 2)
speeds |= FC_PORTSPEED_4GBIT;
}
} else if (IS_QLA2031(ha))
speeds = FC_PORTSPEED_16GBIT|FC_PORTSPEED_8GBIT|
FC_PORTSPEED_4GBIT;
else if (IS_QLA25XX(ha) || IS_QLAFX00(ha))
speeds = FC_PORTSPEED_8GBIT|FC_PORTSPEED_4GBIT|
FC_PORTSPEED_2GBIT|FC_PORTSPEED_1GBIT;
else if (IS_QLA24XX_TYPE(ha))
speed = FC_PORTSPEED_4GBIT | FC_PORTSPEED_2GBIT |
FC_PORTSPEED_1GBIT;
speeds = FC_PORTSPEED_4GBIT|FC_PORTSPEED_2GBIT|
FC_PORTSPEED_1GBIT;
else if (IS_QLA23XX(ha))
speed = FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT;
else if (IS_QLAFX00(ha))
speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT |
FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT;
else if (IS_QLA27XX(ha))
speed = FC_PORTSPEED_32GBIT | FC_PORTSPEED_16GBIT |
FC_PORTSPEED_8GBIT;
speeds = FC_PORTSPEED_2GBIT|FC_PORTSPEED_1GBIT;
else
speed = FC_PORTSPEED_1GBIT;
fc_host_supported_speeds(vha->host) = speed;
speeds = FC_PORTSPEED_1GBIT;
fc_host_supported_speeds(vha->host) = speeds;
}
qla2x00t-32gbit/qla_bsg.c
+59 -13
View File
@@ -1,4 +1,4 @@
/*
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2014 QLogic Corporation
*
@@ -113,8 +113,7 @@ qla24xx_fcp_prio_cfg_valid(scsi_qla_host_t *vha,
return 0;
}
if (bcode[0] != 'H' || bcode[1] != 'Q' || bcode[2] != 'O' ||
bcode[3] != 'S') {
if (memcmp(bcode, "HQOS", 4)) {
/* Invalid FCP priority data header*/
ql_dbg(ql_dbg_user, vha, 0x7052,
"Invalid FCP Priority data header. bcode=0x%x.\n",
@@ -1091,7 +1090,7 @@ static int qla84xx_updatefw(struct bsg_job *bsg_job)
}
flag = bsg_request->rqst_data.h_vendor.vendor_cmd[1];
fw_ver = le32_to_cpu(*((uint32_t *)((uint32_t *)fw_buf + 2)));
fw_ver = get_unaligned_le32((uint32_t *)fw_buf + 2);
mn->entry_type = VERIFY_CHIP_IOCB_TYPE;
mn->entry_count = 1;
@@ -1407,7 +1406,7 @@ static int qla24xx_iidma(struct bsg_job *bsg_job)
if (rval) {
ql_log(ql_log_warn, vha, 0x704c,
"iIDMA cmd failed for %8phN -- "
"iiDMA cmd failed for %8phN -- "
"%04x %x %04x %04x.\n", fcport->port_name,
rval, fcport->fp_speed, mb[0], mb[1]);
rval = (DID_ERROR << 16);
@@ -1469,7 +1468,8 @@ static int qla2x00_optrom_setup(struct bsg_job *bsg_job,
start == (ha->flt_region_fw * 4))
valid = 1;
else if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha))
IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha))
valid = 1;
if (!valid) {
ql_log(ql_log_warn, vha, 0x7058,
@@ -2045,7 +2045,7 @@ static int qlafx00_mgmt_cmd(struct bsg_job *bsg_job)
/* Dump the vendor information */
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose , vha, 0x70cf,
(uint8_t *)piocb_rqst, sizeof(struct qla_mt_iocb_rqst_fx00));
piocb_rqst, sizeof(*piocb_rqst));
if (!vha->flags.online) {
ql_log(ql_log_warn, vha, 0x70d0,
@@ -2250,7 +2250,7 @@ static int qla27xx_get_flash_upd_cap(struct bsg_job *bsg_job)
struct qla_hw_data *ha = vha->hw;
struct qla_flash_update_caps cap;
if (!(IS_QLA27XX(ha)))
if (!(IS_QLA27XX(ha)) && !IS_QLA28XX(ha))
return -EPERM;
memset(&cap, 0, sizeof(cap));
@@ -2286,7 +2286,7 @@ static int qla27xx_set_flash_upd_cap(struct bsg_job *bsg_job)
uint64_t online_fw_attr = 0;
struct qla_flash_update_caps cap;
if (!(IS_QLA27XX(ha)))
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return -EPERM;
memset(&cap, 0, sizeof(cap));
@@ -2337,7 +2337,7 @@ static int qla27xx_get_bbcr_data(struct bsg_job *bsg_job)
uint8_t domain, area, al_pa, state;
int rval;
if (!(IS_QLA27XX(ha)))
if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return -EPERM;
memset(&bbcr, 0, sizeof(bbcr));
@@ -2425,8 +2425,8 @@ static int qla2x00_get_priv_stats(struct bsg_job *bsg_job)
rval = qla24xx_get_isp_stats(base_vha, stats, stats_dma, options);
if (rval == QLA_SUCCESS) {
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e3,
(uint8_t *)stats, sizeof(*stats));
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose, vha, 0x70e5,
stats, sizeof(*stats));
sg_copy_from_buffer(bsg_job->reply_payload.sg_list,
bsg_job->reply_payload.sg_cnt, stats, sizeof(*stats));
}
@@ -2458,7 +2458,8 @@ static int qla2x00_do_dport_diagnostics(struct bsg_job *bsg_job)
int rval;
struct qla_dport_diag *dd;
if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
!IS_QLA28XX(vha->hw))
return -EPERM;
dd = kmalloc(sizeof(*dd), GFP_KERNEL);
@@ -2492,6 +2493,48 @@ static int qla2x00_do_dport_diagnostics(struct bsg_job *bsg_job)
return 0;
}
#ifndef NEW_LIBFC_API
static int qla2x00_get_flash_image_status(struct fc_bsg_job *bsg_job)
#else
static int qla2x00_get_flash_image_status(struct bsg_job *bsg_job)
#endif
{
scsi_qla_host_t *vha = shost_priv(fc_bsg_to_shost(bsg_job));
struct fc_bsg_reply *bsg_reply = bsg_job->reply;
struct qla_hw_data *ha = vha->hw;
struct qla_active_regions regions = { };
struct active_regions active_regions = { };
qla28xx_get_aux_images(vha, &active_regions);
regions.global_image = active_regions.global;
if (IS_QLA28XX(ha)) {
qla27xx_get_active_image(vha, &active_regions);
regions.board_config = active_regions.aux.board_config;
regions.vpd_nvram = active_regions.aux.vpd_nvram;
regions.npiv_config_0_1 = active_regions.aux.npiv_config_0_1;
regions.npiv_config_2_3 = active_regions.aux.npiv_config_2_3;
}
ql_dbg(ql_dbg_user, vha, 0x70e1,
"%s(%lu): FW=%u BCFG=%u VPDNVR=%u NPIV01=%u NPIV02=%u\n",
__func__, vha->host_no, regions.global_image,
regions.board_config, regions.vpd_nvram,
regions.npiv_config_0_1, regions.npiv_config_2_3);
sg_copy_from_buffer(bsg_job->reply_payload.sg_list,
bsg_job->reply_payload.sg_cnt, &regions, sizeof(regions));
bsg_reply->reply_data.vendor_reply.vendor_rsp[0] = EXT_STATUS_OK;
bsg_reply->reply_payload_rcv_len = sizeof(regions);
bsg_reply->result = DID_OK << 16;
bsg_job->reply_len = sizeof(struct fc_bsg_reply);
bsg_job_done(bsg_job, bsg_reply->result,
bsg_reply->reply_payload_rcv_len);
return 0;
}
#ifndef NEW_LIBFC_API
static int qla2x00_process_vendor_specific(struct fc_bsg_job *bsg_job)
#else
@@ -2568,6 +2611,9 @@ static int qla2x00_process_vendor_specific(struct bsg_job *bsg_job)
case QL_VND_DPORT_DIAGNOSTICS:
return qla2x00_do_dport_diagnostics(bsg_job);
case QL_VND_SS_GET_FLASH_IMAGE_STATUS:
return qla2x00_get_flash_image_status(bsg_job);
default:
return -ENOSYS;
}
qla2x00t-32gbit/qla_bsg.h
+11
View File
@@ -31,6 +31,7 @@
#define QL_VND_GET_PRIV_STATS 0x18
#define QL_VND_DPORT_DIAGNOSTICS 0x19
#define QL_VND_GET_PRIV_STATS_EX 0x1A
#define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E
/* BSG Vendor specific subcode returns */
#define EXT_STATUS_OK 0
@@ -279,4 +280,14 @@ struct qla_dport_diag {
#define QLA_DPORT_RESULT 0x0
#define QLA_DPORT_START 0x2
/* active images in flash */
struct qla_active_regions {
uint8_t global_image;
uint8_t board_config;
uint8_t vpd_nvram;
uint8_t npiv_config_0_1;
uint8_t npiv_config_2_3;
uint8_t reserved[32];
} __packed;
#endif
qla2x00t-32gbit/qla_dbg.c
+93 -97
View File
@@ -111,30 +111,25 @@ int
qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
uint32_t ram_dwords, void **nxt)
{
int rval;
uint32_t cnt, stat, timer, dwords, idx;
uint16_t mb0;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
dma_addr_t dump_dma = ha->gid_list_dma;
uint32_t *dump = (uint32_t *)ha->gid_list;
uint32_t *chunk = (void *)ha->gid_list;
uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
uint32_t stat;
ulong i, j, timer = 6000000;
int rval = QLA_FUNCTION_FAILED;
rval = QLA_SUCCESS;
mb0 = 0;
WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
if (i + dwords > ram_dwords)
dwords = ram_dwords - i;
dwords = qla2x00_gid_list_size(ha) / 4;
for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
cnt += dwords, addr += dwords) {
if (cnt + dwords > ram_dwords)
dwords = ram_dwords - cnt;
WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
WRT_REG_WORD(&reg->mailbox1, LSW(addr));
WRT_REG_WORD(&reg->mailbox8, MSW(addr));
WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
WRT_REG_WORD(&reg->mailbox2, MSW(LSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox3, LSW(LSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
@@ -145,76 +140,76 @@ qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
ha->flags.mbox_int = 0;
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
while (timer--) {
udelay(5);
stat = RD_REG_DWORD(&reg->host_status);
if (stat & HSRX_RISC_INT) {
stat &= 0xff;
/* Check for pending interrupts. */
if (!(stat & HSRX_RISC_INT))
continue;
if (stat == 0x1 || stat == 0x2 ||
stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_REG_WORD(&reg->mailbox0);
RD_REG_WORD(&reg->mailbox1);
WRT_REG_DWORD(&reg->hccr,
HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
break;
}
stat &= 0xff;
if (stat != 0x1 && stat != 0x2 &&
stat != 0x10 && stat != 0x11) {
/* Clear this intr; it wasn't a mailbox intr */
WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
continue;
}
udelay(5);
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
rval = RD_REG_WORD(&reg->mailbox0) & MBS_MASK;
WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
break;
}
ha->flags.mbox_int = 1;
*nxt = ram + i;
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb0 & MBS_MASK;
for (idx = 0; idx < dwords; idx++)
ram[cnt + idx] = IS_QLA27XX(ha) ?
le32_to_cpu(dump[idx]) : swab32(dump[idx]);
} else {
rval = QLA_FUNCTION_FAILED;
if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
/* no interrupt, timed out*/
return rval;
}
if (rval) {
/* error completion status */
return rval;
}
for (j = 0; j < dwords; j++) {
ram[i + j] =
(IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
chunk[j] : swab32(chunk[j]);
}
}
*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
return rval;
*nxt = ram + i;
return QLA_SUCCESS;
}
int
qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
uint32_t ram_dwords, void **nxt)
{
int rval;
uint32_t cnt, stat, timer, dwords, idx;
uint16_t mb0;
int rval = QLA_FUNCTION_FAILED;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
dma_addr_t dump_dma = ha->gid_list_dma;
uint32_t *dump = (uint32_t *)ha->gid_list;
uint32_t *chunk = (void *)ha->gid_list;
uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
uint32_t stat;
ulong i, j, timer = 6000000;
rval = QLA_SUCCESS;
mb0 = 0;
WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
dwords = qla2x00_gid_list_size(ha) / 4;
for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
cnt += dwords, addr += dwords) {
if (cnt + dwords > ram_dwords)
dwords = ram_dwords - cnt;
for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
if (i + dwords > ram_dwords)
dwords = ram_dwords - i;
WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
WRT_REG_WORD(&reg->mailbox1, LSW(addr));
WRT_REG_WORD(&reg->mailbox8, MSW(addr));
WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
WRT_REG_WORD(&reg->mailbox2, MSW(LSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox3, LSW(LSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
@@ -223,45 +218,48 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
ha->flags.mbox_int = 0;
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
while (timer--) {
udelay(5);
stat = RD_REG_DWORD(&reg->host_status);
if (stat & HSRX_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2 ||
stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
/* Check for pending interrupts. */
if (!(stat & HSRX_RISC_INT))
continue;
mb0 = RD_REG_WORD(&reg->mailbox0);
WRT_REG_DWORD(&reg->hccr,
HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
break;
}
/* Clear this intr; it wasn't a mailbox intr */
stat &= 0xff;
if (stat != 0x1 && stat != 0x2 &&
stat != 0x10 && stat != 0x11) {
WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
continue;
}
udelay(5);
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
rval = RD_REG_WORD(&reg->mailbox0) & MBS_MASK;
WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(&reg->hccr);
break;
}
ha->flags.mbox_int = 1;
*nxt = ram + i;
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb0 & MBS_MASK;
for (idx = 0; idx < dwords; idx++)
ram[cnt + idx] = IS_QLA27XX(ha) ?
le32_to_cpu(dump[idx]) : swab32(dump[idx]);
} else {
rval = QLA_FUNCTION_FAILED;
if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
/* no interrupt, timed out*/
return rval;
}
if (rval) {
/* error completion status */
return rval;
}
for (j = 0; j < dwords; j++) {
ram[i + j] =
(IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
chunk[j] : swab32(chunk[j]);
}
}
*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
return rval;
*nxt = ram + i;
return QLA_SUCCESS;
}
static int
@@ -669,7 +667,8 @@ qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
struct qla2xxx_mq_chain *mq = ptr;
device_reg_t *reg;
if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha))
return ptr;
mq = ptr;
@@ -2521,7 +2520,7 @@ qla83xx_fw_dump_failed:
/****************************************************************************/
static inline int
ql_mask_match(uint32_t level)
ql_mask_match(uint level)
{
return (level & ql2xextended_error_logging) == level;
}
@@ -2540,7 +2539,7 @@ ql_mask_match(uint32_t level)
* msg: The message to be displayed.
*/
void
ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
ql_dbg(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@@ -2583,8 +2582,7 @@ ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
* msg: The message to be displayed.
*/
void
ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
const char *fmt, ...)
ql_dbg_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@@ -2620,7 +2618,7 @@ ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
* msg: The message to be displayed.
*/
void
ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
ql_log(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@@ -2678,8 +2676,7 @@ ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
* msg: The message to be displayed.
*/
void
ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
const char *fmt, ...)
ql_log_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
{
va_list va;
struct va_format vaf;
@@ -2719,7 +2716,7 @@ ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
}
void
ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
{
int i;
struct qla_hw_data *ha = vha->hw;
@@ -2741,13 +2738,12 @@ ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
ql_dbg(level, vha, id, "Mailbox registers:\n");
for (i = 0; i < 6; i++, mbx_reg++)
ql_dbg(level, vha, id,
"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg));
"mbox[%d] %#04x\n", i, RD_REG_WORD(mbx_reg));
}
void
ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
uint8_t *buf, uint size)
ql_dump_buffer(uint level, scsi_qla_host_t *vha, uint id, void *buf, uint size)
{
uint cnt;
qla2x00t-32gbit/qla_dbg.h
+5 -5
View File
@@ -318,20 +318,20 @@ struct qla2xxx_fw_dump {
* as compared to other log levels.
*/
extern int ql_errlev;
extern uint ql_errlev;
void __attribute__((format (printf, 4, 5)))
ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
void __attribute__((format (printf, 4, 5)))
ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
qla2x00t-32gbit/qla_def.h
+136 -51
View File
@@ -560,6 +560,7 @@ typedef struct srb {
int rc;
int retry_count;
struct completion comp;
wait_queue_head_t *cwaitq;
union {
struct srb_iocb iocb_cmd;
#ifndef NEW_LIBFC_API
@@ -1051,6 +1052,7 @@ struct mbx_cmd_32 {
#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
#define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
@@ -1221,6 +1223,10 @@ struct mbx_cmd_32 {
#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
#define QLA27XX_DEFAULT_IMAGE 0
#define QLA27XX_PRIMARY_IMAGE 1
#define QLA27XX_SECONDARY_IMAGE 2
@@ -2691,6 +2697,7 @@ struct ct_fdmiv2_hba_attributes {
#define FDMI_PORT_SPEED_8GB 0x10
#define FDMI_PORT_SPEED_16GB 0x20
#define FDMI_PORT_SPEED_32GB 0x40
#define FDMI_PORT_SPEED_64GB 0x80
#define FDMI_PORT_SPEED_UNKNOWN 0x8000
#define FC_CLASS_2 0x04
@@ -3149,10 +3156,10 @@ struct rsp_que;
struct isp_operations {
int (*pci_config) (struct scsi_qla_host *);
void (*reset_chip) (struct scsi_qla_host *);
int (*reset_chip)(struct scsi_qla_host *);
int (*chip_diag) (struct scsi_qla_host *);
void (*config_rings) (struct scsi_qla_host *);
void (*reset_adapter) (struct scsi_qla_host *);
int (*reset_adapter)(struct scsi_qla_host *);
int (*nvram_config) (struct scsi_qla_host *);
void (*update_fw_options) (struct scsi_qla_host *);
int (*load_risc) (struct scsi_qla_host *, uint32_t *);
@@ -3178,9 +3185,9 @@ struct isp_operations {
void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
uint32_t);
uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
uint32_t);
void (*fw_dump) (struct scsi_qla_host *, int);
@@ -3189,9 +3196,9 @@ struct isp_operations {
int (*beacon_off) (struct scsi_qla_host *);
void (*beacon_blink) (struct scsi_qla_host *);
uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
void *(*read_optrom)(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
uint32_t);
int (*get_flash_version) (struct scsi_qla_host *, void *);
@@ -3387,7 +3394,8 @@ struct qla_tc_param {
#define QLA_MQ_SIZE 32
#define QLA_MAX_QUEUES 256
#define ISP_QUE_REG(ha, id) \
((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
((ha->mqenable || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
((void __iomem *)ha->iobase))
#define QLA_REQ_QUE_ID(tag) \
@@ -3640,6 +3648,8 @@ struct qla_hw_data {
uint32_t rida_fmt2:1;
uint32_t purge_mbox:1;
uint32_t n2n_bigger:1;
uint32_t secure_adapter:1;
uint32_t secure_fw:1;
} flags;
uint16_t max_exchg;
@@ -3722,6 +3732,7 @@ struct qla_hw_data {
#define PORT_SPEED_8GB 0x04
#define PORT_SPEED_16GB 0x05
#define PORT_SPEED_32GB 0x06
#define PORT_SPEED_64GB 0x07
#define PORT_SPEED_10GB 0x13
uint16_t link_data_rate; /* F/W operating speed */
uint16_t set_data_rate; /* Set by user */
@@ -3748,6 +3759,11 @@ struct qla_hw_data {
#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
uint32_t isp_type;
#define DT_ISP2100 BIT_0
@@ -3772,7 +3788,12 @@ struct qla_hw_data {
#define DT_ISP2071 BIT_19
#define DT_ISP2271 BIT_20
#define DT_ISP2261 BIT_21
#define DT_ISP_LAST (DT_ISP2261 << 1)
#define DT_ISP2061 BIT_22
#define DT_ISP2081 BIT_23
#define DT_ISP2089 BIT_24
#define DT_ISP2281 BIT_25
#define DT_ISP2289 BIT_26
#define DT_ISP_LAST (DT_ISP2289 << 1)
uint32_t device_type;
#define DT_T10_PI BIT_25
@@ -3807,6 +3828,8 @@ struct qla_hw_data {
#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
IS_QLA6312(ha) || IS_QLA6322(ha))
@@ -3816,6 +3839,7 @@ struct qla_hw_data {
#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
#define IS_QLA84XX(ha) (IS_QLA8432(ha))
#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
IS_QLA84XX(ha))
#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
@@ -3824,14 +3848,15 @@ struct qla_hw_data {
#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
IS_QLA8044(ha) || IS_QLA27XX(ha))
IS_QLA8044(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha))
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha))
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha))
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
@@ -3842,28 +3867,34 @@ struct qla_hw_data {
#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
IS_QLA27XX(ha))
#define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_BIDI_CAPABLE(ha) \
(IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
/* Bit 21 of fw_attributes decides the MCTP capabilities */
#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
((ha)->fw_attributes_ext[0] & BIT_0))
#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
(((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
IS_QLA28XX(ha))
#define IS_EXCHG_OFFLD_CAPABLE(ha) \
(IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
(IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
(IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
(IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
IS_QLA27XX(ha) || IS_QLA28XX(ha))
#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
IS_QLA83XX(ha) || IS_QLA27XX(ha))
IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
/* HBA serial number */
uint8_t serial0;
@@ -3907,6 +3938,9 @@ struct qla_hw_data {
void *sfp_data;
dma_addr_t sfp_data_dma;
void *flt;
dma_addr_t flt_dma;
#define XGMAC_DATA_SIZE 4096
void *xgmac_data;
dma_addr_t xgmac_data_dma;
@@ -4018,18 +4052,23 @@ struct qla_hw_data {
uint8_t fw_seriallink_options[4];
uint16_t fw_seriallink_options24[4];
uint8_t serdes_version[3];
uint8_t mpi_version[3];
uint32_t mpi_capabilities;
uint8_t phy_version[3];
uint8_t pep_version[3];
/* Firmware dump template */
void *fw_dump_template;
uint32_t fw_dump_template_len;
/* Firmware dump information. */
struct fwdt {
void *template;
ulong length;
ulong dump_size;
} fwdt[2];
struct qla2xxx_fw_dump *fw_dump;
uint32_t fw_dump_len;
int fw_dumped;
u32 fw_dump_alloc_len;
bool fw_dumped;
bool fw_dump_mpi;
unsigned long fw_dump_cap_flags;
#define RISC_PAUSE_CMPL 0
#define DMA_SHUTDOWN_CMPL 1
@@ -4068,7 +4107,6 @@ struct qla_hw_data {
uint16_t product_id[4];
uint8_t model_number[16+1];
#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
char model_desc[80];
uint8_t adapter_id[16+1];
@@ -4108,22 +4146,28 @@ struct qla_hw_data {
uint32_t fdt_protect_sec_cmd;
uint32_t fdt_wrt_sts_reg_cmd;
uint32_t flt_region_flt;
uint32_t flt_region_fdt;
uint32_t flt_region_boot;
uint32_t flt_region_boot_sec;
uint32_t flt_region_fw;
uint32_t flt_region_fw_sec;
uint32_t flt_region_vpd_nvram;
uint32_t flt_region_vpd;
uint32_t flt_region_vpd_sec;
uint32_t flt_region_nvram;
uint32_t flt_region_npiv_conf;
uint32_t flt_region_gold_fw;
uint32_t flt_region_fcp_prio;
uint32_t flt_region_bootload;
uint32_t flt_region_img_status_pri;
uint32_t flt_region_img_status_sec;
struct {
uint32_t flt_region_flt;
uint32_t flt_region_fdt;
uint32_t flt_region_boot;
uint32_t flt_region_boot_sec;
uint32_t flt_region_fw;
uint32_t flt_region_fw_sec;
uint32_t flt_region_vpd_nvram;
uint32_t flt_region_vpd_nvram_sec;
uint32_t flt_region_vpd;
uint32_t flt_region_vpd_sec;
uint32_t flt_region_nvram;
uint32_t flt_region_nvram_sec;
uint32_t flt_region_npiv_conf;
uint32_t flt_region_gold_fw;
uint32_t flt_region_fcp_prio;
uint32_t flt_region_bootload;
uint32_t flt_region_img_status_pri;
uint32_t flt_region_img_status_sec;
uint32_t flt_region_aux_img_status_pri;
uint32_t flt_region_aux_img_status_sec;
};
uint8_t active_image;
/* Needed for BEACON */
@@ -4216,8 +4260,8 @@ struct qla_hw_data {
struct qlt_hw_data tgt;
int allow_cna_fw_dump;
uint32_t fw_ability_mask;
uint16_t min_link_speed;
uint16_t max_speed_sup;
uint16_t min_supported_speed;
uint16_t max_supported_speed;
/* DMA pool for the DIF bundling buffers */
struct dma_pool *dif_bundl_pool;
@@ -4244,9 +4288,20 @@ struct qla_hw_data {
atomic_t zio_threshold;
uint16_t last_zio_threshold;
#define DEFAULT_ZIO_THRESHOLD 5
};
struct active_regions {
uint8_t global;
struct {
uint8_t board_config;
uint8_t vpd_nvram;
uint8_t npiv_config_0_1;
uint8_t npiv_config_2_3;
} aux;
};
#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
#define FW_ABILITY_MAX_SPEED_16G 0x0
#define FW_ABILITY_MAX_SPEED_32G 0x1
@@ -4334,6 +4389,7 @@ typedef struct scsi_qla_host {
#define N2N_LOGIN_NEEDED 30
#define IOCB_WORK_ACTIVE 31
#define SET_ZIO_THRESHOLD_NEEDED 32
#define ISP_ABORT_TO_ROM 33
unsigned long pci_flags;
#define PFLG_DISCONNECTED 0 /* PCI device removed */
@@ -4448,7 +4504,7 @@ typedef struct scsi_qla_host {
int fcport_count;
wait_queue_head_t fcport_waitQ;
wait_queue_head_t vref_waitq;
uint8_t min_link_speed_feat;
uint8_t min_supported_speed;
uint8_t n2n_node_name[WWN_SIZE];
uint8_t n2n_port_name[WWN_SIZE];
uint16_t n2n_id;
@@ -4460,14 +4516,21 @@ typedef struct scsi_qla_host {
struct qla27xx_image_status {
uint8_t image_status_mask;
uint16_t generation_number;
uint8_t reserved[3];
uint8_t ver_minor;
uint16_t generation;
uint8_t ver_major;
uint8_t ver_minor;
uint8_t bitmap; /* 28xx only */
uint8_t reserved[2];
uint32_t checksum;
uint32_t signature;
} __packed;
/* 28xx aux image status bimap values */
#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
#define SET_VP_IDX 1
#define SET_AL_PA 2
#define RESET_VP_IDX 3
@@ -4514,6 +4577,24 @@ struct qla2_sgx {
} \
}
#define SFUB_CHECKSUM_SIZE 4
struct secure_flash_update_block {
uint32_t block_info;
uint32_t signature_lo;
uint32_t signature_hi;
uint32_t signature_upper[0x3e];
};
struct secure_flash_update_block_pk {
uint32_t block_info;
uint32_t signature_lo;
uint32_t signature_hi;
uint32_t signature_upper[0x3e];
uint32_t public_key[0x41];
};
/*
* Macros to help code, maintain, etc.
*/
@@ -4614,6 +4695,7 @@ struct qla2_sgx {
#define OPTROM_SIZE_81XX 0x400000
#define OPTROM_SIZE_82XX 0x800000
#define OPTROM_SIZE_83XX 0x1000000
#define OPTROM_SIZE_28XX 0x2000000
#define OPTROM_BURST_SIZE 0x1000
#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
@@ -4710,10 +4792,13 @@ struct sff_8247_a0 {
#define AUTO_DETECT_SFP_SUPPORT(_vha)\
(ql2xautodetectsfp && !_vha->vp_idx && \
(IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw)))
IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \
IS_QLA28XX(_vha->hw)))
#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
(IS_QLA27XX(_ha) || IS_QLA83XX(_ha)))
(IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
#define SAVE_TOPO(_ha) { \
if (_ha->current_topology) \
qla2x00t-32gbit/qla_dfs.c
+3 -3
View File
@@ -386,7 +386,7 @@ qla_dfs_naqp_write(struct file *file, const char __user *buffer,
int rc = 0;
unsigned long num_act_qp;
if (!(IS_QLA27XX(ha) || IS_QLA83XX(ha))) {
if (!(IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))) {
pr_err("host%ld: this adapter does not support Multi Q.",
vha->host_no);
return -EINVAL;
@@ -438,7 +438,7 @@ qla2x00_dfs_setup(scsi_qla_host_t *vha)
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha))
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
goto out;
if (!ha->fce)
goto out;
@@ -474,7 +474,7 @@ create_nodes:
ha->tgt.dfs_tgt_sess = debugfs_create_file("tgt_sess",
S_IRUSR, ha->dfs_dir, vha, &dfs_tgt_sess_ops);
if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
ha->tgt.dfs_naqp = debugfs_create_file("naqp",
0400, ha->dfs_dir, vha, &dfs_naqp_ops);
out:
qla2x00t-32gbit/qla_fw.h
+28 -3
View File
@@ -1526,13 +1526,31 @@ struct qla_flt_header {
#define FLT_REG_VPD_SEC_27XX_2 0xD8
#define FLT_REG_VPD_SEC_27XX_3 0xDA
/* 28xx */
#define FLT_REG_AUX_IMG_PRI_28XX 0x125
#define FLT_REG_AUX_IMG_SEC_28XX 0x126
#define FLT_REG_VPD_SEC_28XX_0 0x10C
#define FLT_REG_VPD_SEC_28XX_1 0x10E
#define FLT_REG_VPD_SEC_28XX_2 0x110
#define FLT_REG_VPD_SEC_28XX_3 0x112
#define FLT_REG_NVRAM_SEC_28XX_0 0x10D
#define FLT_REG_NVRAM_SEC_28XX_1 0x10F
#define FLT_REG_NVRAM_SEC_28XX_2 0x111
#define FLT_REG_NVRAM_SEC_28XX_3 0x113
struct qla_flt_region {
uint32_t code;
uint16_t code;
uint8_t attribute;
uint8_t reserved;
uint32_t size;
uint32_t start;
uint32_t end;
};
#define FLT_REGION_SIZE 16
#define FLT_MAX_REGIONS 0xFF
#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
/* Flash NPIV Configuration Table ********************************************/
struct qla_npiv_header {
@@ -1722,6 +1740,10 @@ struct access_chip_rsp_84xx {
#define LR_DIST_FW_SHIFT (LR_DIST_FW_POS - LR_DIST_NV_POS)
#define LR_DIST_FW_FIELD(x) ((x) << LR_DIST_FW_SHIFT & 0xf000)
/* FAC semaphore defines */
#define FAC_SEMAPHORE_UNLOCK 0
#define FAC_SEMAPHORE_LOCK 1
struct nvram_81xx {
/* NVRAM header. */
uint8_t id[4];
@@ -1768,7 +1790,7 @@ struct nvram_81xx {
uint16_t reserved_6_3[14];
/* Offset 192. */
uint8_t min_link_speed;
uint8_t min_supported_speed;
uint8_t reserved_7_0;
uint16_t reserved_7[31];
@@ -2016,6 +2038,8 @@ struct ex_init_cb_81xx {
#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
#define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
#define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
/* FCP priority config defines *************************************/
/* operations */
@@ -2090,6 +2114,7 @@ struct qla_fcp_prio_cfg {
#define FA_NPIV_CONF1_ADDR_81 0xD2000
/* 83XX Flash locations -- occupies second 8MB region. */
#define FA_FLASH_LAYOUT_ADDR_83 0xFC400
#define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
#define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
#endif
qla2x00t-32gbit/qla_gbl.h
+49 -40
View File
@@ -18,14 +18,14 @@ extern int qla2100_pci_config(struct scsi_qla_host *);
extern int qla2300_pci_config(struct scsi_qla_host *);
extern int qla24xx_pci_config(scsi_qla_host_t *);
extern int qla25xx_pci_config(scsi_qla_host_t *);
extern void qla2x00_reset_chip(struct scsi_qla_host *);
extern void qla24xx_reset_chip(struct scsi_qla_host *);
extern int qla2x00_reset_chip(struct scsi_qla_host *);
extern int qla24xx_reset_chip(struct scsi_qla_host *);
extern int qla2x00_chip_diag(struct scsi_qla_host *);
extern int qla24xx_chip_diag(struct scsi_qla_host *);
extern void qla2x00_config_rings(struct scsi_qla_host *);
extern void qla24xx_config_rings(struct scsi_qla_host *);
extern void qla2x00_reset_adapter(struct scsi_qla_host *);
extern void qla24xx_reset_adapter(struct scsi_qla_host *);
extern int qla2x00_reset_adapter(struct scsi_qla_host *);
extern int qla24xx_reset_adapter(struct scsi_qla_host *);
extern int qla2x00_nvram_config(struct scsi_qla_host *);
extern int qla24xx_nvram_config(struct scsi_qla_host *);
extern int qla81xx_nvram_config(struct scsi_qla_host *);
@@ -93,7 +93,6 @@ extern int qla2xxx_mctp_dump(scsi_qla_host_t *);
extern int
qla2x00_alloc_outstanding_cmds(struct qla_hw_data *, struct req_que *);
extern int qla2x00_init_rings(scsi_qla_host_t *);
extern uint8_t qla27xx_find_valid_image(struct scsi_qla_host *);
extern struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *,
int, int, bool);
extern int qla2xxx_delete_qpair(struct scsi_qla_host *, struct qla_qpair *);
@@ -108,6 +107,11 @@ int qla24xx_fcport_handle_login(struct scsi_qla_host *, fc_port_t *);
int qla24xx_detect_sfp(scsi_qla_host_t *vha);
int qla24xx_post_gpdb_work(struct scsi_qla_host *, fc_port_t *, u8);
extern void qla28xx_get_aux_images(struct scsi_qla_host *,
struct active_regions *);
extern void qla27xx_get_active_image(struct scsi_qla_host *,
struct active_regions *);
void qla2x00_async_prlo_done(struct scsi_qla_host *, fc_port_t *,
uint16_t *);
extern int qla2x00_post_async_prlo_work(struct scsi_qla_host *, fc_port_t *,
@@ -118,6 +122,7 @@ int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport);
int qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *);
void qla_rscn_replay(fc_port_t *fcport);
extern bool qla24xx_risc_firmware_invalid(uint32_t *);
/*
* Global Data in qla_os.c source file.
@@ -468,6 +473,8 @@ qla81xx_fac_do_write_enable(scsi_qla_host_t *, int);
extern int
qla81xx_fac_erase_sector(scsi_qla_host_t *, uint32_t, uint32_t);
extern int qla81xx_fac_semaphore_access(scsi_qla_host_t *, int);
extern int
qla2x00_get_xgmac_stats(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t *);
@@ -513,6 +520,14 @@ extern int qla27xx_get_zio_threshold(scsi_qla_host_t *, uint16_t *);
extern int qla27xx_set_zio_threshold(scsi_qla_host_t *, uint16_t);
int qla24xx_res_count_wait(struct scsi_qla_host *, uint16_t *, int);
extern int qla28xx_secure_flash_update(scsi_qla_host_t *, uint16_t, uint16_t,
uint32_t, dma_addr_t, uint32_t);
extern int qla2xxx_read_remote_register(scsi_qla_host_t *, uint32_t,
uint32_t *);
extern int qla2xxx_write_remote_register(scsi_qla_host_t *, uint32_t,
uint32_t);
/*
* Global Function Prototypes in qla_isr.c source file.
*/
@@ -544,19 +559,20 @@ fc_port_t *qla2x00_find_fcport_by_nportid(scsi_qla_host_t *, port_id_t *, u8);
*/
extern void qla2x00_release_nvram_protection(scsi_qla_host_t *);
extern uint32_t *qla24xx_read_flash_data(scsi_qla_host_t *, uint32_t *,
uint32_t, uint32_t);
extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
extern int qla2x00_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t,
uint32_t);
uint32_t, uint32_t);
extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern int qla2x00_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern int qla24xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern int qla25xx_write_nvram_data(scsi_qla_host_t *, void *, uint32_t,
uint32_t);
extern int qla2x00_is_a_vp_did(scsi_qla_host_t *, uint32_t);
bool qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *, uint32_t);
bool qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *, uint16_t);
@@ -576,18 +592,18 @@ extern int qla83xx_restart_nic_firmware(scsi_qla_host_t *);
extern int qla83xx_access_control(scsi_qla_host_t *, uint16_t, uint32_t,
uint32_t, uint16_t *);
extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
extern void *qla2x00_read_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern int qla2x00_write_optrom_data(struct scsi_qla_host *, uint8_t *,
extern int qla2x00_write_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern uint8_t *qla24xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
extern void *qla24xx_read_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
extern int qla24xx_write_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern uint8_t *qla25xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
extern void *qla25xx_read_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern uint8_t *qla8044_read_optrom_data(struct scsi_qla_host *,
uint8_t *, uint32_t, uint32_t);
extern void *qla8044_read_optrom_data(struct scsi_qla_host *,
void *, uint32_t, uint32_t);
extern void qla8044_watchdog(struct scsi_qla_host *vha);
extern int qla2x00_get_flash_version(scsi_qla_host_t *, void *);
@@ -612,20 +628,13 @@ extern void qla82xx_fw_dump(scsi_qla_host_t *, int);
extern void qla8044_fw_dump(scsi_qla_host_t *, int);
extern void qla27xx_fwdump(scsi_qla_host_t *, int);
extern ulong qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *);
extern ulong qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *, void *);
extern int qla27xx_fwdt_template_valid(void *);
extern ulong qla27xx_fwdt_template_size(void *);
extern const void *qla27xx_fwdt_template_default(void);
extern ulong qla27xx_fwdt_template_default_size(void);
extern void qla2x00_dump_regs(scsi_qla_host_t *);
extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
extern void qla2x00_dump_buffer_zipped(uint8_t *, uint32_t);
extern void ql_dump_regs(uint32_t, scsi_qla_host_t *, int32_t);
extern void ql_dump_buffer(uint32_t, scsi_qla_host_t *, int32_t,
uint8_t *, uint32_t);
extern void qla2xxx_dump_post_process(scsi_qla_host_t *, int);
extern void ql_dump_regs(uint, scsi_qla_host_t *, uint);
extern void ql_dump_buffer(uint, scsi_qla_host_t *, uint, void *, uint);
/*
* Global Function Prototypes in qla_gs.c source file.
*/
@@ -724,7 +733,7 @@ extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t);
/* qlafx00 related functions */
extern int qlafx00_pci_config(struct scsi_qla_host *);
extern int qlafx00_initialize_adapter(struct scsi_qla_host *);
extern void qlafx00_soft_reset(scsi_qla_host_t *);
extern int qlafx00_soft_reset(scsi_qla_host_t *);
extern int qlafx00_chip_diag(scsi_qla_host_t *);
extern void qlafx00_config_rings(struct scsi_qla_host *);
extern char *qlafx00_pci_info_str(struct scsi_qla_host *, char *);
@@ -767,16 +776,16 @@ extern int qla82xx_pci_region_offset(struct pci_dev *, int);
extern int qla82xx_iospace_config(struct qla_hw_data *);
/* Initialization related functions */
extern void qla82xx_reset_chip(struct scsi_qla_host *);
extern int qla82xx_reset_chip(struct scsi_qla_host *);
extern void qla82xx_config_rings(struct scsi_qla_host *);
extern void qla82xx_watchdog(scsi_qla_host_t *);
extern int qla82xx_start_firmware(scsi_qla_host_t *);
/* Firmware and flash related functions */
extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *);
extern uint8_t *qla82xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
extern void *qla82xx_read_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern int qla82xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
extern int qla82xx_write_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
/* Mailbox related functions */
@@ -877,7 +886,7 @@ extern void qla8044_clear_drv_active(struct qla_hw_data *);
void qla8044_get_minidump(struct scsi_qla_host *vha);
int qla8044_collect_md_data(struct scsi_qla_host *vha);
extern int qla8044_md_get_template(scsi_qla_host_t *);
extern int qla8044_write_optrom_data(struct scsi_qla_host *, uint8_t *,
extern int qla8044_write_optrom_data(struct scsi_qla_host *, void *,
uint32_t, uint32_t);
extern irqreturn_t qla8044_intr_handler(int, void *);
extern void qla82xx_mbx_completion(scsi_qla_host_t *, uint16_t);
qla2x00t-32gbit/qla_gs.c
+36 -52
View File
@@ -152,8 +152,8 @@ qla2x00_chk_ms_status(scsi_qla_host_t *vha, ms_iocb_entry_t *ms_pkt,
vha->d_id.b.area, vha->d_id.b.al_pa,
comp_status, ct_rsp->header.response);
ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha,
0x2078, (uint8_t *)&ct_rsp->header,
sizeof(struct ct_rsp_hdr));
0x2078, ct_rsp,
offsetof(typeof(*ct_rsp), rsp));
rval = QLA_INVALID_COMMAND;
} else
rval = QLA_SUCCESS;
@@ -1794,7 +1794,7 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha)
if (IS_CNA_CAPABLE(ha))
eiter->a.sup_speed = cpu_to_be32(
FDMI_PORT_SPEED_10GB);
else if (IS_QLA27XX(ha))
else if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
eiter->a.sup_speed = cpu_to_be32(
FDMI_PORT_SPEED_32GB|
FDMI_PORT_SPEED_16GB|
@@ -2373,7 +2373,7 @@ qla2x00_fdmiv2_rpa(scsi_qla_host_t *vha)
if (IS_CNA_CAPABLE(ha))
eiter->a.sup_speed = cpu_to_be32(
FDMI_PORT_SPEED_10GB);
else if (IS_QLA27XX(ha))
else if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
eiter->a.sup_speed = cpu_to_be32(
FDMI_PORT_SPEED_32GB|
FDMI_PORT_SPEED_16GB|
@@ -2783,6 +2783,31 @@ qla24xx_prep_ct_fm_req(struct ct_sns_pkt *p, uint16_t cmd,
return &p->p.req;
}
static uint16_t
qla2x00_port_speed_capability(uint16_t speed)
{
switch (speed) {
case BIT_15:
return PORT_SPEED_1GB;
case BIT_14:
return PORT_SPEED_2GB;
case BIT_13:
return PORT_SPEED_4GB;
case BIT_12:
return PORT_SPEED_10GB;
case BIT_11:
return PORT_SPEED_8GB;
case BIT_10:
return PORT_SPEED_16GB;
case BIT_8:
return PORT_SPEED_32GB;
case BIT_7:
return PORT_SPEED_64GB;
default:
return PORT_SPEED_UNKNOWN;
}
}
/**
* qla2x00_gpsc() - FCS Get Port Speed Capabilities (GPSC) query.
* @vha: HA context
@@ -2855,31 +2880,8 @@ qla2x00_gpsc(scsi_qla_host_t *vha, sw_info_t *list)
}
rval = QLA_FUNCTION_FAILED;
} else {
/* Save port-speed */
switch (be16_to_cpu(ct_rsp->rsp.gpsc.speed)) {
case BIT_15:
list[i].fp_speed = PORT_SPEED_1GB;
break;
case BIT_14:
list[i].fp_speed = PORT_SPEED_2GB;
break;
case BIT_13:
list[i].fp_speed = PORT_SPEED_4GB;
break;
case BIT_12:
list[i].fp_speed = PORT_SPEED_10GB;
break;
case BIT_11:
list[i].fp_speed = PORT_SPEED_8GB;
break;
case BIT_10:
list[i].fp_speed = PORT_SPEED_16GB;
break;
case BIT_8:
list[i].fp_speed = PORT_SPEED_32GB;
break;
}
list->fp_speed = qla2x00_port_speed_capability(
be16_to_cpu(ct_rsp->rsp.gpsc.speed));
ql_dbg(ql_dbg_disc, vha, 0x205b,
"GPSC ext entry - fpn "
"%8phN speeds=%04x speed=%04x.\n",
@@ -3030,6 +3032,8 @@ static void qla24xx_async_gpsc_sp_done(void *s, int res)
ql_dbg(ql_dbg_disc, vha, 0x2053, "Async done-%s res %x, WWPN %s \n",
sp->name, res, wwn_to_str(fcport->port_name));
fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
if (res == QLA_FUNCTION_TIMEOUT)
return;
@@ -3047,29 +3051,8 @@ static void qla24xx_async_gpsc_sp_done(void *s, int res)
goto done;
}
} else {
switch (be16_to_cpu(ct_rsp->rsp.gpsc.speed)) {
case BIT_15:
fcport->fp_speed = PORT_SPEED_1GB;
break;
case BIT_14:
fcport->fp_speed = PORT_SPEED_2GB;
break;
case BIT_13:
fcport->fp_speed = PORT_SPEED_4GB;
break;
case BIT_12:
fcport->fp_speed = PORT_SPEED_10GB;
break;
case BIT_11:
fcport->fp_speed = PORT_SPEED_8GB;
break;
case BIT_10:
fcport->fp_speed = PORT_SPEED_16GB;
break;
case BIT_8:
fcport->fp_speed = PORT_SPEED_32GB;
break;
}
fcport->fp_speed = qla2x00_port_speed_capability(
be16_to_cpu(ct_rsp->rsp.gpsc.speed));
ql_dbg(ql_dbg_disc, vha, 0x2054,
"Async-%s OUT WWPN %s speeds=%04x speed=%04x.\n",
@@ -4378,6 +4361,7 @@ int qla24xx_async_gnnid(scsi_qla_host_t *vha, fc_port_t *fcport)
done_free_sp:
sp->free(sp);
fcport->flags &= ~FCF_ASYNC_SENT;
done:
return rval;
}
qla2x00t-32gbit/qla_init.c
+681 -439
View File
File diff suppressed because it is too large Load Diff
qla2x00t-32gbit/qla_inline.h
+1
View File
@@ -261,6 +261,7 @@ done:
static inline void
qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp)
{
sp->qpair = NULL;
mempool_free(sp, qpair->srb_mempool);
QLA_QPAIR_MARK_NOT_BUSY(qpair);
}
qla2x00t-32gbit/qla_iocb.c
+12 -14
View File
@@ -107,7 +107,7 @@ qla2x00_prep_cont_type0_iocb(struct scsi_qla_host *vha)
cont_pkt = (cont_entry_t *)req->ring_ptr;
/* Load packet defaults. */
*((uint32_t *)(&cont_pkt->entry_type)) = cpu_to_le32(CONTINUE_TYPE);
put_unaligned_le32(CONTINUE_TYPE, &cont_pkt->entry_type);
return (cont_pkt);
}
@@ -136,9 +136,8 @@ qla2x00_prep_cont_type1_iocb(scsi_qla_host_t *vha, struct req_que *req)
cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
/* Load packet defaults. */
*((uint32_t *)(&cont_pkt->entry_type)) = IS_QLAFX00(vha->hw) ?
cpu_to_le32(CONTINUE_A64_TYPE_FX00) :
cpu_to_le32(CONTINUE_A64_TYPE);
put_unaligned_le32(IS_QLAFX00(vha->hw) ? CONTINUE_A64_TYPE_FX00 :
CONTINUE_A64_TYPE, &cont_pkt->entry_type);
return (cont_pkt);
}
@@ -202,8 +201,7 @@ void qla2x00_build_scsi_iocbs_32(srb_t *sp, cmd_entry_t *cmd_pkt,
cmd = GET_CMD_SP(sp);
/* Update entry type to indicate Command Type 2 IOCB */
*((uint32_t *)(&cmd_pkt->entry_type)) =
cpu_to_le32(COMMAND_TYPE);
put_unaligned_le32(COMMAND_TYPE, &cmd_pkt->entry_type);
/* No data transfer */
if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
@@ -260,7 +258,7 @@ void qla2x00_build_scsi_iocbs_64(srb_t *sp, cmd_entry_t *cmd_pkt,
cmd = GET_CMD_SP(sp);
/* Update entry type to indicate Command Type 3 IOCB */
*((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_A64_TYPE);
put_unaligned_le32(COMMAND_A64_TYPE, &cmd_pkt->entry_type);
/* No data transfer */
if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
@@ -467,7 +465,7 @@ qla2x00_start_iocbs(struct scsi_qla_host *vha, struct req_que *req)
req->ring_ptr++;
/* Set chip new ring index. */
if (ha->mqenable || IS_QLA27XX(ha)) {
if (ha->mqenable || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
WRT_REG_DWORD(req->req_q_in, req->ring_index);
} else if (IS_QLA83XX(ha)) {
WRT_REG_DWORD(req->req_q_in, req->ring_index);
@@ -596,7 +594,7 @@ qla24xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt,
cmd = GET_CMD_SP(sp);
/* Update entry type to indicate Command Type 3 IOCB */
*((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_TYPE_6);
put_unaligned_le32(COMMAND_TYPE_6, &cmd_pkt->entry_type);
/* No data transfer */
if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
@@ -711,7 +709,7 @@ qla24xx_build_scsi_iocbs(srb_t *sp, struct cmd_type_7 *cmd_pkt,
cmd = GET_CMD_SP(sp);
/* Update entry type to indicate Command Type 3 IOCB */
*((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_TYPE_7);
put_unaligned_le32(COMMAND_TYPE_7, &cmd_pkt->entry_type);
/* No data transfer */
if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
@@ -1430,7 +1428,7 @@ qla24xx_build_scsi_crc_2_iocbs(srb_t *sp, struct cmd_type_crc_2 *cmd_pkt,
cmd = GET_CMD_SP(sp);
/* Update entry type to indicate Command Type CRC_2 IOCB */
*((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_TYPE_CRC_2);
put_unaligned_le32(COMMAND_TYPE_CRC_2, &cmd_pkt->entry_type);
vha = sp->vha;
ha = vha->hw;
@@ -2332,7 +2330,8 @@ __qla2x00_alloc_iocbs(struct qla_qpair *qpair, srb_t *sp)
if (req->cnt < req_cnt + 2) {
if (qpair->use_shadow_reg)
cnt = *req->out_ptr;
else if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha))
else if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha))
cnt = RD_REG_DWORD(&reg->isp25mq.req_q_out);
else if (IS_P3P_TYPE(ha))
cnt = RD_REG_DWORD(&reg->isp82.req_q_out);
@@ -3769,8 +3768,7 @@ qla25xx_build_bidir_iocb(srb_t *sp, struct scsi_qla_host *vha,
#endif
/*Update entry type to indicate bidir command */
*((uint32_t *)(&cmd_pkt->entry_type)) =
cpu_to_le32(COMMAND_BIDIRECTIONAL);
put_unaligned_le32(COMMAND_BIDIRECTIONAL, &cmd_pkt->entry_type);
/* Set the transfer direction, in this set both flags
* Also set the BD_WRAP_BACK flag, firmware will take care
qla2x00t-32gbit/qla_isr.c
+65 -52
View File
@@ -378,7 +378,7 @@ qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
static const char *const link_speeds[] = {
"1", "2", "?", "4", "8", "16", "32", "10"
};
#define QLA_LAST_SPEED 7
#define QLA_LAST_SPEED (ARRAY_SIZE(link_speeds) - 1)
if (IS_QLA2100(ha) || IS_QLA2200(ha))
return link_speeds[0];
@@ -720,12 +720,15 @@ skip_rio:
break;
case MBA_SYSTEM_ERR: /* System Error */
mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) ?
RD_REG_WORD(&reg24->mailbox7) : 0;
ql_log(ql_log_warn, vha, 0x5003,
"ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
"mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
ha->fw_dump_mpi =
(IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
RD_REG_WORD(&reg24->mailbox7) & BIT_8;
ha->isp_ops->fw_dump(vha, 1);
ha->flags.fw_init_done = 0;
QLA_FW_STOPPED(ha);
@@ -1384,7 +1387,7 @@ qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
le16_to_cpu(mbx->status_flags));
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
(uint8_t *)mbx, sizeof(*mbx));
mbx, sizeof(*mbx));
goto logio_done;
}
@@ -1532,7 +1535,7 @@ qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
bsg_reply->reply_payload_rcv_len = 0;
}
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
(uint8_t *)pkt, sizeof(*pkt));
pkt, sizeof(*pkt));
} else {
res = DID_OK << 16;
bsg_reply->reply_payload_rcv_len =
@@ -1676,7 +1679,7 @@ qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
memcpy(bsg_job->reply + sizeof(struct fc_bsg_reply),
fw_status, sizeof(fw_status));
ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
(uint8_t *)pkt, sizeof(*pkt));
pkt, sizeof(*pkt));
}
else {
res = DID_OK << 16;
@@ -1720,7 +1723,7 @@ qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
fcport->d_id.b.area, fcport->d_id.b.al_pa,
logio->entry_status);
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
(uint8_t *)logio, sizeof(*logio));
logio, sizeof(*logio));
goto logio_done;
}
@@ -1866,8 +1869,8 @@ qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
}
if (iocb->u.tmf.data != QLA_SUCCESS)
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
(uint8_t *)sts, sizeof(*sts));
ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, sp->vha, 0x5055,
sts, sizeof(*sts));
sp->done(sp, 0);
}
@@ -1989,6 +1992,52 @@ static void qla_ctrlvp_completed(scsi_qla_host_t *vha, struct req_que *req,
sp->done(sp, rval);
}
/* Process a single response queue entry. */
static void qla2x00_process_response_entry(struct scsi_qla_host *vha,
struct rsp_que *rsp,
sts_entry_t *pkt)
{
sts21_entry_t *sts21_entry;
sts22_entry_t *sts22_entry;
uint16_t handle_cnt;
uint16_t cnt;
switch (pkt->entry_type) {
case STATUS_TYPE:
qla2x00_status_entry(vha, rsp, pkt);
break;
case STATUS_TYPE_21:
sts21_entry = (sts21_entry_t *)pkt;
handle_cnt = sts21_entry->handle_count;
for (cnt = 0; cnt < handle_cnt; cnt++)
qla2x00_process_completed_request(vha, rsp->req,
sts21_entry->handle[cnt]);
break;
case STATUS_TYPE_22:
sts22_entry = (sts22_entry_t *)pkt;
handle_cnt = sts22_entry->handle_count;
for (cnt = 0; cnt < handle_cnt; cnt++)
qla2x00_process_completed_request(vha, rsp->req,
sts22_entry->handle[cnt]);
break;
case STATUS_CONT_TYPE:
qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
break;
case MBX_IOCB_TYPE:
qla2x00_mbx_iocb_entry(vha, rsp->req, (struct mbx_entry *)pkt);
break;
case CT_IOCB_TYPE:
qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
break;
default:
/* Type Not Supported. */
ql_log(ql_log_warn, vha, 0x504a,
"Received unknown response pkt type %x entry status=%x.\n",
pkt->entry_type, pkt->entry_status);
break;
}
}
/**
* qla2x00_process_response_queue() - Process response queue entries.
* @rsp: response queue
@@ -2000,8 +2049,6 @@ qla2x00_process_response_queue(struct rsp_que *rsp)
struct qla_hw_data *ha = rsp->hw;
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
sts_entry_t *pkt;
uint16_t handle_cnt;
uint16_t cnt;
vha = pci_get_drvdata(ha->pdev);
@@ -2026,42 +2073,7 @@ qla2x00_process_response_queue(struct rsp_que *rsp)
continue;
}
switch (pkt->entry_type) {
case STATUS_TYPE:
qla2x00_status_entry(vha, rsp, pkt);
break;
case STATUS_TYPE_21:
handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
for (cnt = 0; cnt < handle_cnt; cnt++) {
qla2x00_process_completed_request(vha, rsp->req,
((sts21_entry_t *)pkt)->handle[cnt]);
}
break;
case STATUS_TYPE_22:
handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
for (cnt = 0; cnt < handle_cnt; cnt++) {
qla2x00_process_completed_request(vha, rsp->req,
((sts22_entry_t *)pkt)->handle[cnt]);
}
break;
case STATUS_CONT_TYPE:
qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
break;
case MBX_IOCB_TYPE:
qla2x00_mbx_iocb_entry(vha, rsp->req,
(struct mbx_entry *)pkt);
break;
case CT_IOCB_TYPE:
qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
break;
default:
/* Type Not Supported. */
ql_log(ql_log_warn, vha, 0x504a,
"Received unknown response pkt type %x "
"entry status=%x.\n",
pkt->entry_type, pkt->entry_status);
break;
}
qla2x00_process_response_entry(vha, rsp, pkt);
((response_t *)pkt)->signature = RESPONSE_PROCESSED;
wmb();
}
@@ -3038,7 +3050,8 @@ process_err:
qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
break;
case ABTS_RECV_24XX:
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
/* ensure that the ATIO queue is empty */
qlt_handle_abts_recv(vha, rsp,
(response_t *)pkt);
@@ -3111,7 +3124,7 @@ qla2xxx_check_risc_status(scsi_qla_host_t *vha)
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha))
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return;
rval = QLA_SUCCESS;
@@ -3644,7 +3657,7 @@ msix_register_fail:
}
/* Enable MSI-X vector for response queue update for queue 0 */
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (ha->msixbase && ha->mqiobase &&
(ha->max_rsp_queues > 1 || ha->max_req_queues > 1 ||
ql2xmqsupport))
@@ -3686,7 +3699,7 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
/* If possible, enable MSI-X. */
if (ql2xenablemsix == 0 || (!IS_QLA2432(ha) && !IS_QLA2532(ha) &&
!IS_QLA8432(ha) && !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
!IS_QLAFX00(ha) && !IS_QLA27XX(ha)))
!IS_QLAFX00(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)))
goto skip_msi;
if (ql2xenablemsix == 2)
@@ -3725,7 +3738,7 @@ skip_msix:
if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
!IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
!IS_QLA27XX(ha))
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
goto skip_msi;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)
qla2x00t-32gbit/qla_mbx.c
+244 -77
View File
@@ -638,14 +638,15 @@ qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
mcp->out_mb |= MBX_4;
}
mcp->in_mb = MBX_0;
mcp->in_mb = MBX_1|MBX_0;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x1023,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
"Failed=%x mb[0]=%x mb[1]=%x.\n",
rval, mcp->mb[0], mcp->mb[1]);
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
"Done %s.\n", __func__);
@@ -660,7 +661,7 @@ static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
{
uint16_t mb4 = BIT_0;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
mb4 |= ha->long_range_distance << LR_DIST_FW_POS;
return mb4;
@@ -670,7 +671,7 @@ static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
{
uint16_t mb4 = BIT_0;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
struct nvram_81xx *nv = ha->nvram;
mb4 |= LR_DIST_FW_FIELD(nv->enhanced_features);
@@ -715,7 +716,7 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
mcp->mb[4] = 0;
ha->flags.using_lr_setting = 0;
if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
IS_QLA27XX(ha)) {
IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (ql2xautodetectsfp) {
if (ha->flags.detected_lr_sfp) {
mcp->mb[4] |=
@@ -734,19 +735,20 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
}
}
if (ql2xnvmeenable && IS_QLA27XX(ha))
if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
mcp->mb[4] |= NVME_ENABLE_FLAG;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
struct nvram_81xx *nv = ha->nvram;
/* set minimum speed if specified in nvram */
if (nv->min_link_speed >= 2 &&
nv->min_link_speed <= 5) {
if (nv->min_supported_speed >= 2 &&
nv->min_supported_speed <= 5) {
mcp->mb[4] |= BIT_4;
mcp->mb[11] = nv->min_link_speed;
mcp->mb[11] |= nv->min_supported_speed & 0xF;
mcp->out_mb |= MBX_11;
mcp->in_mb |= BIT_5;
vha->min_link_speed_feat = nv->min_link_speed;
vha->min_supported_speed =
nv->min_supported_speed;
}
}
@@ -774,34 +776,39 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x1026,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
} else {
if (IS_FWI2_CAPABLE(ha)) {
ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
ql_dbg(ql_dbg_mbx, vha, 0x119a,
"fw_ability_mask=%x.\n", ha->fw_ability_mask);
ql_dbg(ql_dbg_mbx, vha, 0x1027,
"exchanges=%x.\n", mcp->mb[1]);
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ha->max_speed_sup = mcp->mb[2] & BIT_0;
ql_dbg(ql_dbg_mbx, vha, 0x119b,
"Maximum speed supported=%s.\n",
ha->max_speed_sup ? "32Gps" : "16Gps");
if (vha->min_link_speed_feat) {
ha->min_link_speed = mcp->mb[5];
ql_dbg(ql_dbg_mbx, vha, 0x119c,
"Minimum speed set=%s.\n",
mcp->mb[5] == 5 ? "32Gps" :
mcp->mb[5] == 4 ? "16Gps" :
mcp->mb[5] == 3 ? "8Gps" :
mcp->mb[5] == 2 ? "4Gps" :
"unknown");
}
}
}
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
"Done.\n");
return rval;
}
if (!IS_FWI2_CAPABLE(ha))
goto done;
ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
ql_dbg(ql_dbg_mbx, vha, 0x119a,
"fw_ability_mask=%x.\n", ha->fw_ability_mask);
ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
ha->max_supported_speed == 0 ? "16Gps" :
ha->max_supported_speed == 1 ? "32Gps" :
ha->max_supported_speed == 2 ? "64Gps" : "unknown");
if (vha->min_supported_speed) {
ha->min_supported_speed = mcp->mb[5] &
(BIT_0 | BIT_1 | BIT_2);
ql_dbg(ql_dbg_mbx, vha, 0x119c,
"min_supported_speed=%s.\n",
ha->min_supported_speed == 6 ? "64Gps" :
ha->min_supported_speed == 5 ? "32Gps" :
ha->min_supported_speed == 4 ? "16Gps" :
ha->min_supported_speed == 3 ? "8Gps" :
ha->min_supported_speed == 2 ? "4Gps" : "unknown");
}
}
done:
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
"Done %s.\n", __func__);
return rval;
}
@@ -1057,10 +1064,10 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
if (IS_FWI2_CAPABLE(ha))
mcp->in_mb |= MBX_17|MBX_16|MBX_15;
if (IS_QLA27XX(ha))
if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->in_mb |=
MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
mcp->flags = 0;
mcp->tov = MBX_TOV_SECONDS;
@@ -1126,7 +1133,10 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
}
}
if (IS_QLA27XX(ha)) {
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
ha->serdes_version[0] = mcp->mb[7] & 0xff;
ha->serdes_version[1] = mcp->mb[8] >> 8;
ha->serdes_version[2] = mcp->mb[8] & 0xff;
ha->mpi_version[0] = mcp->mb[10] & 0xff;
ha->mpi_version[1] = mcp->mb[11] >> 8;
ha->mpi_version[2] = mcp->mb[11] & 0xff;
@@ -1137,6 +1147,13 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
if (IS_QLA28XX(ha)) {
if (mcp->mb[16] & BIT_10) {
ql_log(ql_log_info, vha, 0xffff,
"FW support secure flash updates\n");
ha->flags.secure_fw = 1;
}
}
}
failed:
@@ -1642,7 +1659,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
if (IS_FWI2_CAPABLE(vha->hw))
mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
if (IS_QLA27XX(vha->hw))
if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
mcp->in_mb |= MBX_15;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
@@ -1696,7 +1713,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
}
}
if (IS_QLA27XX(vha->hw))
if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
vha->bbcr = mcp->mb[15];
}
@@ -1812,7 +1829,7 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
}
/* 1 and 2 should normally be captured. */
mcp->in_mb = MBX_2|MBX_1|MBX_0;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
/* mb3 is additional info about the installed SFP. */
mcp->in_mb |= MBX_3;
mcp->buf_size = size;
@@ -1823,10 +1840,20 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
if (rval != QLA_SUCCESS) {
/*EMPTY*/
ql_dbg(ql_dbg_mbx, vha, 0x104d,
"Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
"Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
if (ha->init_cb) {
ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
0x0104d, ha->init_cb, sizeof(*ha->init_cb));
}
if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
}
} else {
if (IS_QLA27XX(ha)) {
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
ql_dbg(ql_dbg_mbx, vha, 0x119d,
"Invalid SFP/Validation Failed\n");
@@ -2080,7 +2107,7 @@ qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
/*EMPTY*/
ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
} else {
if (IS_QLA27XX(ha)) {
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
ql_dbg(ql_dbg_mbx, vha, 0x119e,
"Invalid SFP/Validation Failed\n");
@@ -2863,7 +2890,8 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
mcp->out_mb = MBX_0;
mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->in_mb |= MBX_12;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
@@ -2888,7 +2916,8 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
ha->orig_fw_iocb_count = mcp->mb[10];
if (ha->flags.npiv_supported)
ha->max_npiv_vports = mcp->mb[11];
if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha))
ha->fw_max_fcf_count = mcp->mb[12];
}
@@ -3327,7 +3356,7 @@ qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
mbx_cmd_t *mcp = &mc;
if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
!IS_QLA27XX(vha->hw))
!IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
@@ -3366,7 +3395,7 @@ qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
mbx_cmd_t *mcp = &mc;
if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
!IS_QLA27XX(vha->hw))
!IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
@@ -3635,7 +3664,8 @@ qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
"Entered %s.\n", __func__);
if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
!IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
if (unlikely(pci_channel_offline(vha->hw->pdev)))
@@ -3748,7 +3778,7 @@ qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
rval = qla2x00_mailbox_command(vha, mcp);
/* Return mailbox statuses. */
if (mb != NULL) {
if (mb) {
mb[0] = mcp->mb[0];
mb[1] = mcp->mb[1];
mb[3] = mcp->mb[3];
@@ -3783,7 +3813,7 @@ qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
mcp->mb[0] = MBC_PORT_PARAMS;
mcp->mb[1] = loop_id;
mcp->mb[2] = BIT_0;
mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
mcp->mb[3] = port_speed & 0x3F;
mcp->mb[9] = vha->vp_idx;
mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_3|MBX_1|MBX_0;
@@ -3792,7 +3822,7 @@ qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
rval = qla2x00_mailbox_command(vha, mcp);
/* Return mailbox statuses. */
if (mb != NULL) {
if (mb) {
mb[0] = mcp->mb[0];
mb[1] = mcp->mb[1];
mb[3] = mcp->mb[3];
@@ -4231,7 +4261,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
"Dump of Verify Request.\n");
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
(uint8_t *)mn, sizeof(*mn));
mn, sizeof(*mn));
rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
if (rval != QLA_SUCCESS) {
@@ -4243,7 +4273,7 @@ qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
"Dump of Verify Response.\n");
ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
(uint8_t *)mn, sizeof(*mn));
mn, sizeof(*mn));
status[0] = le16_to_cpu(mn->p.rsp.comp_status);
status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
@@ -4319,7 +4349,7 @@ qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
mcp->mb[12] = req->qos;
mcp->mb[11] = req->vp_idx;
mcp->mb[13] = req->rid;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->mb[15] = 0;
mcp->mb[4] = req->id;
@@ -4333,9 +4363,10 @@ qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
mcp->flags = MBX_DMA_OUT;
mcp->tov = MBX_TOV_SECONDS * 2;
if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha))
mcp->in_mb |= MBX_1;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
mcp->out_mb |= MBX_15;
/* debug q create issue in SR-IOV */
mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
@@ -4344,7 +4375,7 @@ qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
spin_lock_irqsave(&ha->hardware_lock, flags);
if (!(req->options & BIT_0)) {
WRT_REG_DWORD(req->req_q_in, 0);
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
WRT_REG_DWORD(req->req_q_out, 0);
}
spin_unlock_irqrestore(&ha->hardware_lock, flags);
@@ -4388,7 +4419,7 @@ qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
mcp->mb[5] = rsp->length;
mcp->mb[14] = rsp->msix->entry;
mcp->mb[13] = rsp->rid;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->mb[15] = 0;
mcp->mb[4] = rsp->id;
@@ -4405,7 +4436,7 @@ qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
if (IS_QLA81XX(ha)) {
mcp->out_mb |= MBX_12|MBX_11|MBX_10;
mcp->in_mb |= MBX_1;
} else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
} else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
mcp->in_mb |= MBX_1;
/* debug q create issue in SR-IOV */
@@ -4415,7 +4446,7 @@ qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
spin_lock_irqsave(&ha->hardware_lock, flags);
if (!(rsp->options & BIT_0)) {
WRT_REG_DWORD(rsp->rsp_q_out, 0);
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
WRT_REG_DWORD(rsp->rsp_q_in, 0);
}
@@ -4473,7 +4504,7 @@ qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
"Entered %s.\n", __func__);
if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
!IS_QLA27XX(vha->hw))
!IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
@@ -4505,7 +4536,7 @@ qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
mbx_cmd_t *mcp = &mc;
if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
!IS_QLA27XX(vha->hw))
!IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
@@ -4540,7 +4571,7 @@ qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
mbx_cmd_t *mcp = &mc;
if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
!IS_QLA27XX(vha->hw))
!IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
@@ -4570,6 +4601,42 @@ qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
return rval;
}
int
qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
{
int rval = QLA_SUCCESS;
mbx_cmd_t mc;
mbx_cmd_t *mcp = &mc;
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return rval;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
"Entered %s.\n", __func__);
mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
FAC_OPT_CMD_UNLOCK_SEMAPHORE);
mcp->out_mb = MBX_1|MBX_0;
mcp->in_mb = MBX_1|MBX_0;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x10e3,
"Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
"Done %s.\n", __func__);
}
return rval;
}
int
qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
{
@@ -4819,10 +4886,10 @@ qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x10e9,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
if (mcp->mb[0] == MBS_COMMAND_ERROR &&
mcp->mb[1] == 0x22)
if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
/* sfp is not there */
rval = QLA_INTERFACE_ERROR;
}
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
"Done %s.\n", __func__);
@@ -5162,13 +5229,14 @@ qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
mcp->mb[3] = MSW(data);
mcp->mb[8] = MSW(risc_addr);
mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_0;
mcp->in_mb = MBX_1|MBX_0;
mcp->tov = 30;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x1101,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
"Failed=%x mb[0]=%x mb[1]=%x.\n",
rval, mcp->mb[0], mcp->mb[1]);
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
"Done %s.\n", __func__);
@@ -5279,7 +5347,7 @@ qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
mcp->out_mb = MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_2|MBX_1|MBX_0;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->in_mb |= MBX_4|MBX_3;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
@@ -5317,7 +5385,7 @@ qla2x00_get_data_rate(scsi_qla_host_t *vha)
mcp->mb[1] = QLA_GET_DATA_RATE;
mcp->out_mb = MBX_1|MBX_0;
mcp->in_mb = MBX_2|MBX_1|MBX_0;
if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
mcp->in_mb |= MBX_3;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
@@ -5347,7 +5415,7 @@ qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
"Entered %s.\n", __func__);
if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
!IS_QLA27XX(ha))
!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return QLA_FUNCTION_FAILED;
mcp->mb[0] = MBC_GET_PORT_CONFIG;
mcp->out_mb = MBX_0;
@@ -5843,7 +5911,7 @@ qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
mbx_cmd_t mc;
mbx_cmd_t *mcp = &mc;
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
@@ -5918,7 +5986,7 @@ qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
struct qla_hw_data *ha = vha->hw;
unsigned long retry_max_time = jiffies + (2 * HZ);
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
@@ -5968,7 +6036,7 @@ qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
mbx_cmd_t *mcp = &mc;
struct qla_hw_data *ha = vha->hw;
if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
if (!IS_QLA83XX(ha))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
@@ -6102,7 +6170,8 @@ qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
mbx_cmd_t *mcp = &mc;
dma_addr_t dd_dma;
if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
!IS_QLA28XX(vha->hw))
return QLA_FUNCTION_FAILED;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
@@ -6508,3 +6577,101 @@ int qla24xx_res_count_wait(struct scsi_qla_host *vha,
done:
return rval;
}
int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
uint32_t sfub_len)
{
int rval;
mbx_cmd_t mc;
mbx_cmd_t *mcp = &mc;
mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
mcp->mb[1] = opts;
mcp->mb[2] = region;
mcp->mb[3] = MSW(len);
mcp->mb[4] = LSW(len);
mcp->mb[5] = MSW(sfub_dma_addr);
mcp->mb[6] = LSW(sfub_dma_addr);
mcp->mb[7] = MSW(MSD(sfub_dma_addr));
mcp->mb[8] = LSW(MSD(sfub_dma_addr));
mcp->mb[9] = sfub_len;
mcp->out_mb =
MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_2|MBX_1|MBX_0;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
__func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
mcp->mb[2]);
}
return rval;
}
int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
uint32_t data)
{
int rval;
mbx_cmd_t mc;
mbx_cmd_t *mcp = &mc;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
"Entered %s.\n", __func__);
mcp->mb[0] = MBC_WRITE_REMOTE_REG;
mcp->mb[1] = LSW(addr);
mcp->mb[2] = MSW(addr);
mcp->mb[3] = LSW(data);
mcp->mb[4] = MSW(data);
mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_1|MBX_0;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x10e9,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
"Done %s.\n", __func__);
}
return rval;
}
int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
uint32_t *data)
{
int rval;
mbx_cmd_t mc;
mbx_cmd_t *mcp = &mc;
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
"Entered %s.\n", __func__);
mcp->mb[0] = MBC_READ_REMOTE_REG;
mcp->mb[1] = LSW(addr);
mcp->mb[2] = MSW(addr);
mcp->out_mb = MBX_2|MBX_1|MBX_0;
mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
mcp->tov = MBX_TOV_SECONDS;
mcp->flags = 0;
rval = qla2x00_mailbox_command(vha, mcp);
*data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
if (rval != QLA_SUCCESS) {
ql_dbg(ql_dbg_mbx, vha, 0x10e9,
"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
} else {
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
"Done %s.\n", __func__);
}
return rval;
}
qla2x00t-32gbit/qla_mr.c
+22 -24
View File
@@ -628,17 +628,20 @@ qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
*
* Returns 0 on success.
*/
void
int
qlafx00_soft_reset(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
int rval = QLA_FUNCTION_FAILED;
if (unlikely(pci_channel_offline(ha->pdev) &&
ha->flags.pci_channel_io_perm_failure))
return;
return rval;
ha->isp_ops->disable_intrs(ha);
qlafx00_soc_cpu_reset(vha);
return QLA_SUCCESS;
}
/**
@@ -1137,8 +1140,8 @@ qlafx00_find_all_targets(scsi_qla_host_t *vha,
ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
"Listing Target bit map...\n");
ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
0x2089, (uint8_t *)ha->gid_list, 32);
ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
ha->gid_list, 32);
/* Allocate temporary rmtport for any new rmtports discovered. */
new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
@@ -1922,8 +1925,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
phost_info->domainname,
phost_info->hostdriver);
ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
(uint8_t *)phost_info,
sizeof(struct host_system_info));
phost_info, sizeof(*phost_info));
}
}
@@ -1977,7 +1979,7 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
vha->d_id.b.al_pa = pinfo->port_id[2];
qlafx00_update_host_attr(vha, pinfo);
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
(uint8_t *)pinfo, 16);
pinfo, 16);
} else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
struct qlafx00_tgt_node_info *pinfo =
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
@@ -1985,12 +1987,12 @@ qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
fcport->port_type = FCT_TARGET;
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
(uint8_t *)pinfo, 16);
pinfo, 16);
} else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
struct qlafx00_tgt_node_info *pinfo =
(struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
(uint8_t *)pinfo, 16);
pinfo, 16);
memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
} else if (fx_type == FXDISC_ABORT_IOCTL)
fdisc->u.fxiocb.result =
@@ -2262,18 +2264,16 @@ qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
fw_sts_ptr = bsg_job_sense(bsg_job) +
sizeof(struct fc_bsg_reply);
memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
sizeof(struct qla_mt_iocb_rsp_fx00));
memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->fcport->vha, 0x5080,
(uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
sp->vha, 0x5080, pkt, sizeof(*pkt));
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->fcport->vha, 0x5074,
(uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
sp->vha, 0x5074,
fw_sts_ptr, sizeof(fstatus));
res = bsg_reply->result = DID_OK << 16;
bsg_reply->reply_payload_rcv_len =
@@ -2611,7 +2611,7 @@ qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
/* Move sense data. */
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
(uint8_t *)pkt, sizeof(sts_cont_entry_t));
pkt, sizeof(*pkt));
memcpy(sense_ptr, pkt->data, sense_sz);
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
sense_ptr, sense_sz);
@@ -3070,13 +3070,13 @@ qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
if (avail_dsds == 0 && cont == 1) {
cont = 0;
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
REQUEST_ENTRY_SIZE);
sizeof(lcont_pkt));
}
}
if (avail_dsds != 0 && cont == 1) {
memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
REQUEST_ENTRY_SIZE);
sizeof(lcont_pkt));
}
}
@@ -3186,9 +3186,9 @@ qlafx00_start_scsi(srb_t *sp)
lcmd_pkt.entry_status = (uint8_t) rsp->id;
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
(uint8_t *)cmd->cmnd, cmd->cmd_len);
cmd->cmnd, cmd->cmd_len);
ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
(uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
&lcmd_pkt, sizeof(lcmd_pkt));
memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
wmb();
@@ -3472,10 +3472,8 @@ qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
}
ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
sp->vha, 0x3047,
(uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
sizeof(struct fxdisc_entry_fx00));
memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
wmb();
}
qla2x00t-32gbit/qla_nvme.c
+26 -9
View File
@@ -172,12 +172,13 @@ static void qla_nvme_sp_done(void *ptr, int res)
if (!atomic_dec_and_test(&sp->ref_count))
return;
if (res == QLA_SUCCESS)
fd->status = 0;
else
fd->status = NVME_SC_INTERNAL;
fd->rcv_rsplen = nvme->u.nvme.rsp_pyld_len;
if (res == QLA_SUCCESS) {
fd->rcv_rsplen = nvme->u.nvme.rsp_pyld_len;
} else {
fd->rcv_rsplen = 0;
fd->transferred_length = 0;
}
fd->status = 0;
fd->done(fd);
qla2xxx_rel_qpair_sp(sp->qpair, sp);
@@ -201,6 +202,22 @@ static void qla_nvme_abort_work(struct work_struct *work)
if (!ha->flags.fw_started && (fcport && fcport->deleted))
return;
if (ha->flags.host_shutting_down) {
ql_log(ql_log_info, sp->fcport->vha, 0xffff,
"%s Calling done on sp: %p, type: 0x%x, sp->ref_count: 0x%x\n",
__func__, sp, sp->type, atomic_read(&sp->ref_count));
sp->done(sp, 0);
return;
}
if (atomic_read(&sp->ref_count) == 0) {
WARN_ON(1);
ql_log(ql_log_info, fcport->vha, 0xffff,
"%s: command already aborted on sp: %p\n",
__func__, sp);
return;
}
rval = ha->isp_ops->abort_command(sp);
ql_dbg(ql_dbg_io, fcport->vha, 0x212b,
@@ -440,8 +457,8 @@ static inline int qla2x00_start_nvme_mq(srb_t *sp)
req->ring_ptr++;
}
cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
*((uint32_t *)(&cont_pkt->entry_type)) =
cpu_to_le32(CONTINUE_A64_TYPE);
put_unaligned_le32(CONTINUE_A64_TYPE,
&cont_pkt->entry_type);
cur_dsd = (uint32_t *)cont_pkt->dseg_0_address;
avail_dsds = 5;
@@ -579,7 +596,7 @@ static struct nvme_fc_port_template qla_nvme_fc_transport = {
.fcp_io = qla_nvme_post_cmd,
.fcp_abort = qla_nvme_fcp_abort,
.max_hw_queues = 8,
.max_sgl_segments = 128,
.max_sgl_segments = 1024,
.max_dif_sgl_segments = 64,
.dma_boundary = 0xFFFFFFFF,
.local_priv_sz = 8,
qla2x00t-32gbit/qla_nx.c
+7 -6
View File
@@ -1757,11 +1757,13 @@ qla82xx_pci_config(scsi_qla_host_t *vha)
*
* Returns 0 on success.
*/
void
int
qla82xx_reset_chip(scsi_qla_host_t *vha)
{
struct qla_hw_data *ha = vha->hw;
ha->isp_ops->disable_intrs(ha);
return QLA_SUCCESS;
}
void qla82xx_config_rings(struct scsi_qla_host *vha)
@@ -2658,8 +2660,8 @@ done:
/*
* Address and length are byte address
*/
uint8_t *
qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
void *
qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
uint32_t offset, uint32_t length)
{
scsi_block_requests(vha->host);
@@ -2767,15 +2769,14 @@ write_done:
}
int
qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
uint32_t offset, uint32_t length)
{
int rval;
/* Suspend HBA. */
scsi_block_requests(vha->host);
rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
length >> 2);
rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
scsi_unblock_requests(vha->host);
/* Convert return ISP82xx to generic */
qla2x00t-32gbit/qla_nx2.c
+4 -4
View File
@@ -559,12 +559,12 @@ exit_lock_error:
/*
* Address and length are byte address
*/
uint8_t *
qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
void *
qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
uint32_t offset, uint32_t length)
{
scsi_block_requests(vha->host);
if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
if (qla8044_read_flash_data(vha, buf, offset, length / 4)
!= QLA_SUCCESS) {
ql_log(ql_log_warn, vha, 0xb08d,
"%s: Failed to read from flash\n",
@@ -3797,7 +3797,7 @@ qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
}
int
qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
uint32_t offset, uint32_t length)
{
int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
qla2x00t-32gbit/qla_os.c
+184 -89
View File
@@ -55,7 +55,7 @@ static struct kmem_cache *ctx_cachep;
/*
* error level for logging
*/
int ql_errlev = ql_log_all;
uint ql_errlev = 0x8001;
static int ql2xenableclass2;
module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
@@ -303,14 +303,14 @@ MODULE_PARM_DESC(qla2xuseresexchforels,
"Reserve 1/2 of emergency exchanges for ELS.\n"
" 0 (default): disabled");
int ql2xprotmask;
static int ql2xprotmask;
module_param(ql2xprotmask, int, 0644);
MODULE_PARM_DESC(ql2xprotmask,
"Override DIF/DIX protection capabilities mask\n"
"Default is 0 which sets protection mask based on "
"capabilities reported by HBA firmware.\n");
int ql2xprotguard;
static int ql2xprotguard;
module_param(ql2xprotguard, int, 0644);
MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
" 0 -- Let HBA firmware decide\n"
@@ -467,7 +467,7 @@ static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
qla_cpu_update(rsp->qpair, raw_smp_processor_id());
ha->base_qpair->pdev = ha->pdev;
if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
}
@@ -766,7 +766,7 @@ qla2x00_sp_free_dma(void *ptr)
}
if (!ctx)
goto end;
return;
if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
/* List assured to be having elements */
@@ -791,12 +791,6 @@ qla2x00_sp_free_dma(void *ptr)
ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
mempool_free(ctx1, ha->ctx_mempool);
}
end:
if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
CMD_SP(cmd) = NULL;
qla2x00_rel_sp(sp);
}
}
void
@@ -804,8 +798,7 @@ qla2x00_sp_compl(void *ptr, int res)
{
srb_t *sp = ptr;
struct scsi_cmnd *cmd = GET_CMD_SP(sp);
cmd->result = res;
wait_queue_head_t *cwaitq = sp->cwaitq;
if (WARN_ON(atomic_read(&sp->ref_count) == 0))
return;
@@ -814,7 +807,12 @@ qla2x00_sp_compl(void *ptr, int res)
return;
sp->free(sp);
cmd->result = res;
CMD_SP(cmd) = NULL;
cmd->scsi_done(cmd);
if (cwaitq)
wake_up(cwaitq);
qla2x00_rel_sp(sp);
}
void
@@ -837,7 +835,7 @@ qla2xxx_qpair_sp_free_dma(void *ptr)
}
if (!ctx)
goto end;
return;
if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
/* List assured to be having elements */
@@ -897,10 +895,6 @@ qla2xxx_qpair_sp_free_dma(void *ptr)
}
sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
}
end:
CMD_SP(cmd) = NULL;
qla2xxx_rel_qpair_sp(sp->qpair, sp);
}
void
@@ -908,8 +902,7 @@ qla2xxx_qpair_sp_compl(void *ptr, int res)
{
srb_t *sp = ptr;
struct scsi_cmnd *cmd = GET_CMD_SP(sp);
cmd->result = res;
wait_queue_head_t *cwaitq = sp->cwaitq;
if (WARN_ON(atomic_read(&sp->ref_count) == 0))
return;
@@ -918,7 +911,12 @@ qla2xxx_qpair_sp_compl(void *ptr, int res)
return;
sp->free(sp);
cmd->result = res;
CMD_SP(cmd) = NULL;
cmd->scsi_done(cmd);
if (cwaitq)
wake_up(cwaitq);
qla2xxx_rel_qpair_sp(sp->qpair, sp);
}
#if defined(RHEL_MAJOR) && RHEL_MAJOR -0 == 6 && RHEL_MINOR -0 >= 2
@@ -1430,7 +1428,6 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd)
vha->host_no, id, lun, sp, cmd, sp->handle);
/* Get a reference to the sp and drop the lock.*/
rval = ha->isp_ops->abort_command(sp);
if (rval) {
if (rval == QLA_FUNCTION_PARAMETER_ERROR)
@@ -1447,37 +1444,46 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd)
}
spin_lock_irqsave(qpair->qp_lock_ptr, flags);
/*
* Clear the slot in the oustanding_cmds array if we can't find the
* command to reclaim the resources.
*/
if (rval == QLA_FUNCTION_PARAMETER_ERROR)
vha->req->outstanding_cmds[sp->handle] = NULL;
/*
* sp->done will do ref_count--
* sp_get() took an extra count above
* Releasing of the SRB and associated command resources
* is managed through ref_count.
* Whether we need to wait for the abort completion or complete
* the abort handler should be based on the ref_count.
*/
sp->done(sp, DID_RESET << 16);
if (atomic_read(&sp->ref_count) > 1) {
/*
* The command is not yet completed. We need to wait for either
* command completion or abort completion.
*/
DECLARE_WAIT_QUEUE_HEAD_ONSTACK(eh_waitq);
uint32_t ratov = ha->r_a_tov/10;
/* Did the command return during mailbox execution? */
if (ret == FAILED && !CMD_SP(cmd))
ret = SUCCESS;
/* Go ahead and release the extra ref_count obtained earlier */
sp->done(sp, DID_RESET << 16);
sp->cwaitq = &eh_waitq;
if (!CMD_SP(cmd))
wait = 0;
spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
/* Wait for the command to be returned. */
if (wait) {
if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
ql_log(ql_log_warn, vha, 0x8006,
"Abort handler timed out cmd=%p.\n", cmd);
if (!wait_event_lock_irq_timeout(eh_waitq,
CMD_SP(cmd) == NULL, *qpair->qp_lock_ptr,
msecs_to_jiffies(4 * ratov * 1000))) {
/*
* The abort got dropped, LOGO will be sent and the
* original command will be completed with CS_TIMEOUT
* completion
*/
ql_dbg(ql_dbg_taskm, vha, 0xffff,
"%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
__func__, ha->r_a_tov);
sp->cwaitq = NULL;
ret = FAILED;
goto end;
}
} else {
/* Command completed while processing the abort */
sp->done(sp, DID_RESET << 16);
}
end:
spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
ql_log(ql_log_info, vha, 0x801c,
"Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
vha->host_no, id, lun, wait, ret);
@@ -2809,6 +2815,24 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha)
ha->device_type |= DT_T10_PI;
ha->fw_srisc_address = RISC_START_ADDRESS_2400;
break;
case PCI_DEVICE_ID_QLOGIC_ISP2081:
case PCI_DEVICE_ID_QLOGIC_ISP2089:
ha->isp_type |= DT_ISP2081;
ha->device_type |= DT_ZIO_SUPPORTED;
ha->device_type |= DT_FWI2;
ha->device_type |= DT_IIDMA;
ha->device_type |= DT_T10_PI;
ha->fw_srisc_address = RISC_START_ADDRESS_2400;
break;
case PCI_DEVICE_ID_QLOGIC_ISP2281:
case PCI_DEVICE_ID_QLOGIC_ISP2289:
ha->isp_type |= DT_ISP2281;
ha->device_type |= DT_ZIO_SUPPORTED;
ha->device_type |= DT_FWI2;
ha->device_type |= DT_IIDMA;
ha->device_type |= DT_T10_PI;
ha->fw_srisc_address = RISC_START_ADDRESS_2400;
break;
}
if (IS_QLA82XX(ha))
@@ -2816,7 +2840,8 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha)
else {
/* Get adapter physical port no from interrupt pin register. */
pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
if (IS_QLA27XX(ha))
if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
IS_QLA27XX(ha) || IS_QLA28XX(ha))
ha->port_no--;
else
ha->port_no = !(ha->port_no & 1);
@@ -2913,7 +2938,11 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
bars = pci_select_bars(pdev, IORESOURCE_MEM);
mem_only = 1;
ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
@@ -2933,6 +2962,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
/* This may fail but that's ok */
pci_enable_pcie_error_reporting(pdev);
/* Turn off T10-DIF when FC-NVMe is enabled */
if (ql2xnvmeenable)
ql2xenabledif = 0;
ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
if (!ha) {
ql_log_pci(ql_log_fatal, pdev, 0x0009,
@@ -2962,7 +2995,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
/* Set EEH reset type to fundamental if required by hba */
if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
IS_QLA83XX(ha) || IS_QLA27XX(ha))
IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
pdev->needs_freset = 1;
ha->prev_topology = 0;
@@ -3141,6 +3174,23 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
ha->nvram_conf_off = ~0;
ha->nvram_data_off = ~0;
} else if (IS_QLA28XX(ha)) {
ha->portnum = PCI_FUNC(ha->pdev->devfn);
ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
ha->mbx_count = MAILBOX_REGISTER_COUNT;
req_length = REQUEST_ENTRY_CNT_24XX;
rsp_length = RESPONSE_ENTRY_CNT_2300;
ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
ha->gid_list_info_size = 8;
ha->optrom_size = OPTROM_SIZE_28XX;
ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
ha->isp_ops = &qla27xx_isp_ops;
ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
ha->nvram_conf_off = ~0;
ha->nvram_data_off = ~0;
}
ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
@@ -3308,7 +3358,8 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
req->req_q_out = &ha->iobase->isp24.req_q_out;
rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
@@ -3634,7 +3685,8 @@ qla2x00_shutdown(struct pci_dev *pdev)
if (ha->eft)
qla2x00_disable_eft_trace(vha);
if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
if (ha->flags.fw_started)
qla2x00_abort_isp_cleanup(vha);
} else {
@@ -3739,7 +3791,8 @@ qla2x00_unmap_iobases(struct qla_hw_data *ha)
if (ha->mqiobase)
iounmap(ha->mqiobase);
if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
ha->msixbase)
iounmap(ha->msixbase);
}
}
@@ -3790,7 +3843,8 @@ qla2x00_remove_one(struct pci_dev *pdev)
}
qla2x00_wait_for_hba_ready(base_vha);
if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
if (ha->flags.fw_started)
qla2x00_abort_isp_cleanup(base_vha);
} else if (!IS_QLAFX00(ha)) {
@@ -3828,8 +3882,6 @@ qla2x00_remove_one(struct pci_dev *pdev)
qla2x00_delete_all_vps(ha, base_vha);
qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
qla2x00_dfs_remove(base_vha);
qla84xx_put_chip(base_vha);
@@ -3918,11 +3970,8 @@ void qla2x00_free_fcports(struct scsi_qla_host *vha)
{
fc_port_t *fcport, *tfcport;
list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
list_del(&fcport->list);
qla2x00_clear_loop_id(fcport);
kfree(fcport);
}
list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
qla2x00_free_fcport(fcport);
}
static inline void
@@ -4280,7 +4329,8 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
ha->npiv_info = NULL;
/* Get consistent memory allocated for EX-INIT-CB. */
if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
&ha->ex_init_cb_dma);
if (!ha->ex_init_cb)
@@ -4323,8 +4373,20 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
goto fail_sfp_data;
}
ha->flt = dma_alloc_coherent(&ha->pdev->dev,
sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
GFP_KERNEL);
if (!ha->flt) {
ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
"Unable to allocate memory for FLT.\n");
goto fail_flt_buffer;
}
return 0;
fail_flt_buffer:
dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
ha->sfp_data, ha->sfp_data_dma);
fail_sfp_data:
kfree(ha->loop_id_map);
fail_loop_id_map:
@@ -4660,6 +4722,9 @@ qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
static void
qla2x00_free_fw_dump(struct qla_hw_data *ha)
{
struct fwdt *fwdt = ha->fwdt;
uint j;
if (ha->fce)
dma_free_coherent(&ha->pdev->dev,
FCE_SIZE, ha->fce, ha->fce_dma);
@@ -4670,8 +4735,6 @@ qla2x00_free_fw_dump(struct qla_hw_data *ha)
if (ha->fw_dump)
vfree(ha->fw_dump);
if (ha->fw_dump_template)
vfree(ha->fw_dump_template);
ha->fce = NULL;
ha->fce_dma = 0;
@@ -4682,8 +4745,13 @@ qla2x00_free_fw_dump(struct qla_hw_data *ha)
ha->fw_dump_reading = 0;
ha->fw_dump = NULL;
ha->fw_dump_len = 0;
ha->fw_dump_template = NULL;
ha->fw_dump_template_len = 0;
for (j = 0; j < 2; j++, fwdt++) {
if (fwdt->template)
vfree(fwdt->template);
fwdt->template = NULL;
fwdt->length = 0;
}
}
/*
@@ -4724,6 +4792,10 @@ qla2x00_mem_free(struct qla_hw_data *ha)
dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
ha->sfp_data_dma);
if (ha->flt)
dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
ha->flt, ha->flt_dma);
if (ha->ms_iocb)
dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
@@ -6743,8 +6815,10 @@ qla2x00_timer(struct timer_list *t)
* FC-NVME
* see if the active AEN count has changed from what was last reported.
*/
if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) !=
ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) {
if (!vha->vp_idx &&
(atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
ha->zio_mode == QLA_ZIO_MODE_6 &&
!ha->flags.host_shutting_down) {
ql_log(ql_log_info, vha, 0x3002,
"nvme: Sched: Set ZIO exchange threshold to %d.\n",
ha->nvme_last_rptd_aen);
@@ -6756,7 +6830,7 @@ qla2x00_timer(struct timer_list *t)
if (!vha->vp_idx &&
(atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
(ha->zio_mode == QLA_ZIO_MODE_6) &&
(IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
(IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
ql_log(ql_log_info, vha, 0x3002,
"Sched: Set ZIO exchange threshold to %d.\n",
ha->last_zio_threshold);
@@ -6802,7 +6876,6 @@ qla2x00_timer(struct timer_list *t)
/* Firmware interface routines. */
#define FW_BLOBS 11
#define FW_ISP21XX 0
#define FW_ISP22XX 1
#define FW_ISP2300 2
@@ -6814,6 +6887,7 @@ qla2x00_timer(struct timer_list *t)
#define FW_ISP2031 8
#define FW_ISP8031 9
#define FW_ISP27XX 10
#define FW_ISP28XX 11
#define FW_FILE_ISP21XX "ql2100_fw.bin"
#define FW_FILE_ISP22XX "ql2200_fw.bin"
@@ -6826,11 +6900,12 @@ qla2x00_timer(struct timer_list *t)
#define FW_FILE_ISP2031 "ql2600_fw.bin"
#define FW_FILE_ISP8031 "ql8300_fw.bin"
#define FW_FILE_ISP27XX "ql2700_fw.bin"
#define FW_FILE_ISP28XX "ql2800_fw.bin"
static DEFINE_MUTEX(qla_fw_lock);
static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
static struct fw_blob qla_fw_blobs[] = {
{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
@@ -6842,6 +6917,8 @@ static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
{ .name = FW_FILE_ISP2031, },
{ .name = FW_FILE_ISP8031, },
{ .name = FW_FILE_ISP27XX, },
{ .name = FW_FILE_ISP28XX, },
{ .name = NULL, },
};
struct fw_blob *
@@ -6872,10 +6949,15 @@ qla2x00_request_firmware(scsi_qla_host_t *vha)
blob = &qla_fw_blobs[FW_ISP8031];
} else if (IS_QLA27XX(ha)) {
blob = &qla_fw_blobs[FW_ISP27XX];
} else if (IS_QLA28XX(ha)) {
blob = &qla_fw_blobs[FW_ISP28XX];
} else {
return NULL;
}
if (!blob->name)
return NULL;
mutex_lock(&qla_fw_lock);
if (blob->fw)
goto out;
@@ -6885,7 +6967,6 @@ qla2x00_request_firmware(scsi_qla_host_t *vha)
"Failed to load firmware image (%s).\n", blob->name);
blob->fw = NULL;
blob = NULL;
goto out;
}
out:
@@ -6896,11 +6977,11 @@ out:
static void
qla2x00_release_firmware(void)
{
int idx;
struct fw_blob *blob;
mutex_lock(&qla_fw_lock);
for (idx = 0; idx < FW_BLOBS; idx++)
release_firmware(qla_fw_blobs[idx].fw);
for (blob = qla_fw_blobs; blob->name; blob++)
release_firmware(blob->fw);
mutex_unlock(&qla_fw_lock);
}
@@ -7335,6 +7416,11 @@ static struct pci_device_id qla2xxx_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
{ 0 },
};
MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
@@ -7376,8 +7462,7 @@ qla2x00_module_init(void)
/* Initialize target kmem_cache and mem_pools */
ret = qlt_init();
if (ret < 0) {
kmem_cache_destroy(srb_cachep);
return ret;
goto destroy_cache;
} else if (ret > 0) {
/*
* If initiator mode is explictly disabled by qlt_init(),
@@ -7401,11 +7486,10 @@ qla2x00_module_init(void)
qla2xxx_transport_template =
fc_attach_transport(&qla2xxx_transport_functions);
if (!qla2xxx_transport_template) {
kmem_cache_destroy(srb_cachep);
ql_log(ql_log_fatal, NULL, 0x0002,
"fc_attach_transport failed...Failing load!.\n");
qlt_exit();
return -ENODEV;
ret = -ENODEV;
goto qlt_exit;
}
apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
@@ -7417,27 +7501,37 @@ qla2x00_module_init(void)
qla2xxx_transport_vport_template =
fc_attach_transport(&qla2xxx_transport_vport_functions);
if (!qla2xxx_transport_vport_template) {
kmem_cache_destroy(srb_cachep);
qlt_exit();
fc_release_transport(qla2xxx_transport_template);
ql_log(ql_log_fatal, NULL, 0x0004,
"fc_attach_transport vport failed...Failing load!.\n");
return -ENODEV;
ret = -ENODEV;
goto unreg_chrdev;
}
ql_log(ql_log_info, NULL, 0x0005,
"QLogic Fibre Channel HBA Driver: %s.\n",
qla2x00_version_str);
ret = pci_register_driver(&qla2xxx_pci_driver);
if (ret) {
kmem_cache_destroy(srb_cachep);
qlt_exit();
fc_release_transport(qla2xxx_transport_template);
fc_release_transport(qla2xxx_transport_vport_template);
ql_log(ql_log_fatal, NULL, 0x0006,
"pci_register_driver failed...ret=%d Failing load!.\n",
ret);
goto release_vport_transport;
}
return ret;
release_vport_transport:
fc_release_transport(qla2xxx_transport_vport_template);
unreg_chrdev:
if (apidev_major >= 0)
unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
fc_release_transport(qla2xxx_transport_template);
qlt_exit:
qlt_exit();
destroy_cache:
kmem_cache_destroy(srb_cachep);
return ret;
}
/**
@@ -7446,14 +7540,15 @@ qla2x00_module_init(void)
static void __exit
qla2x00_module_exit(void)
{
unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
pci_unregister_driver(&qla2xxx_pci_driver);
qla2x00_release_firmware();
kmem_cache_destroy(srb_cachep);
qlt_exit();
kmem_cache_destroy(ctx_cachep);
fc_release_transport(qla2xxx_transport_template);
fc_release_transport(qla2xxx_transport_vport_template);
if (apidev_major >= 0)
unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
fc_release_transport(qla2xxx_transport_template);
qlt_exit();
kmem_cache_destroy(srb_cachep);
}
module_init(qla2x00_module_init);
qla2x00t-32gbit/qla_sup.c
+665 -312
View File
File diff suppressed because it is too large Load Diff
qla2x00t-32gbit/qla_target.c
+4 -3
View File
@@ -6985,7 +6985,7 @@ qlt_24xx_config_rings(struct scsi_qla_host *vha)
RD_REG_DWORD(ISP_ATIO_Q_OUT(vha));
if (ha->flags.msix_enabled) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
if (IS_QLA2071(ha)) {
/* 4 ports Baker: Enable Interrupt Handshake */
icb->msix_atio = 0;
@@ -7000,7 +7000,7 @@ qlt_24xx_config_rings(struct scsi_qla_host *vha)
}
} else {
/* INTx|MSI */
if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
icb->msix_atio = 0;
icb->firmware_options_2 |= BIT_26;
ql_dbg(ql_dbg_init, vha, 0xf072,
@@ -7249,7 +7249,8 @@ qlt_probe_one_stage1(struct scsi_qla_host *base_vha, struct qla_hw_data *ha)
if (!QLA_TGT_MODE_ENABLED())
return;
if ((ql2xenablemsix == 0) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
if ((ql2xenablemsix == 0) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
IS_QLA28XX(ha)) {
ISP_ATIO_Q_IN(base_vha) = &ha->mqiobase->isp25mq.atio_q_in;
ISP_ATIO_Q_OUT(base_vha) = &ha->mqiobase->isp25mq.atio_q_out;
} else {
qla2x00t-32gbit/qla_tmpl.c
+192 -255
View File
@@ -7,103 +7,9 @@
#include "qla_def.h"
#include "qla_tmpl.h"
/* note default template is in big endian */
static const uint32_t ql27xx_fwdt_default_template[] = {
0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x04010000, 0x14000000, 0x00000000,
0x02000000, 0x44000000, 0x09010000, 0x10000000,
0x00000000, 0x02000000, 0x01010000, 0x1c000000,
0x00000000, 0x02000000, 0x00600000, 0x00000000,
0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
0x02000000, 0x00600000, 0x00000000, 0xcc000000,
0x01010000, 0x1c000000, 0x00000000, 0x02000000,
0x10600000, 0x00000000, 0xd4000000, 0x01010000,
0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
0x00000060, 0xf0000000, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x00700000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x10700000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x40700000, 0x041000c0,
0x01010000, 0x1c000000, 0x00000000, 0x02000000,
0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
0x18000000, 0x00000000, 0x02000000, 0x007c0000,
0x040300c4, 0x00010000, 0x18000000, 0x00000000,
0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
0x00000000, 0xc0000000, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x007c0000, 0x04200000,
0x0b010000, 0x18000000, 0x00000000, 0x02000000,
0x0c000000, 0x00000000, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x0a000000, 0x04200080, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x00300000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x10300000, 0x041000c0, 0x00010000, 0x18000000,
0x00000000, 0x02000000, 0x20300000, 0x041000c0,
0x00010000, 0x18000000, 0x00000000, 0x02000000,
0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
0x00000000, 0x02000000, 0x06010000, 0x1c000000,
0x00000000, 0x02000000, 0x01000000, 0x00000200,
0xff230200, 0x06010000, 0x1c000000, 0x00000000,
0x02000000, 0x02000000, 0x00001000, 0x00000000,
0x07010000, 0x18000000, 0x00000000, 0x02000000,
0x00000000, 0x01000000, 0x07010000, 0x18000000,
0x00000000, 0x02000000, 0x00000000, 0x02000000,
0x07010000, 0x18000000, 0x00000000, 0x02000000,
0x00000000, 0x03000000, 0x0d010000, 0x14000000,
0x00000000, 0x02000000, 0x00000000, 0xff000000,
0x10000000, 0x00000000, 0x00000080,
};
static inline void __iomem *
qla27xx_isp_reg(struct scsi_qla_host *vha)
{
return &vha->hw->iobase->isp24;
}
#define ISPREG(vha) (&(vha)->hw->iobase->isp24)
#define IOBAR(reg) offsetof(typeof(*(reg)), iobase_addr)
#define IOBASE(vha) IOBAR(ISPREG(vha))
static inline void
qla27xx_insert16(uint16_t value, void *buf, ulong *len)
@@ -128,7 +34,6 @@ qla27xx_insert32(uint32_t value, void *buf, ulong *len)
static inline void
qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
{
if (buf && mem && size) {
buf += *len;
memcpy(buf, mem, size);
@@ -190,9 +95,9 @@ static inline void
qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
uint offset, uint32_t data, void *buf)
{
__iomem void *window = (void __iomem *)reg + offset;
if (buf) {
void __iomem *window = (void __iomem *)reg + offset;
WRT_REG_DWORD(window, data);
}
}
@@ -205,7 +110,7 @@ qla27xx_read_window(__iomem struct device_reg_24xx *reg,
void __iomem *window = (void __iomem *)reg + offset;
void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
qla27xx_write_reg(reg, IOBAR(reg), addr, buf);
while (count--) {
qla27xx_insert32(addr, buf, len);
readn(window, buf, len);
@@ -224,7 +129,7 @@ qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
static inline struct qla27xx_fwdt_entry *
qla27xx_next_entry(struct qla27xx_fwdt_entry *ent)
{
return (void *)ent + ent->hdr.size;
return (void *)ent + le32_to_cpu(ent->hdr.size);
}
static struct qla27xx_fwdt_entry *
@@ -254,12 +159,14 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t256.base_addr);
uint offset = ent->t256.pci_offset;
ulong count = le16_to_cpu(ent->t256.reg_count);
uint width = ent->t256.reg_width;
ql_dbg(ql_dbg_misc, vha, 0xd200,
"%s: rdio t1 [%lx]\n", __func__, *len);
qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
ent->t256.reg_count, ent->t256.reg_width, buf, len);
qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
return qla27xx_next_entry(ent);
}
@@ -268,12 +175,14 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t257.base_addr);
uint offset = ent->t257.pci_offset;
ulong data = le32_to_cpu(ent->t257.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd201,
"%s: wrio t1 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
return qla27xx_next_entry(ent);
}
@@ -282,13 +191,17 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint banksel = ent->t258.banksel_offset;
ulong bank = le32_to_cpu(ent->t258.bank);
ulong addr = le32_to_cpu(ent->t258.base_addr);
uint offset = ent->t258.pci_offset;
uint count = le16_to_cpu(ent->t258.reg_count);
uint width = ent->t258.reg_width;
ql_dbg(ql_dbg_misc, vha, 0xd202,
"%s: rdio t2 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
ent->t258.reg_count, ent->t258.reg_width, buf, len);
qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
return qla27xx_next_entry(ent);
}
@@ -297,13 +210,17 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = le32_to_cpu(ent->t259.base_addr);
uint banksel = ent->t259.banksel_offset;
ulong bank = le32_to_cpu(ent->t259.bank);
uint offset = ent->t259.pci_offset;
ulong data = le32_to_cpu(ent->t259.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd203,
"%s: wrio t2 [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
return qla27xx_next_entry(ent);
}
@@ -312,12 +229,12 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t260.pci_offset;
ql_dbg(ql_dbg_misc, vha, 0xd204,
"%s: rdpci [%lx]\n", __func__, *len);
qla27xx_insert32(ent->t260.pci_offset, buf, len);
qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
qla27xx_insert32(offset, buf, len);
qla27xx_read_reg(ISPREG(vha), offset, buf, len);
return qla27xx_next_entry(ent);
}
@@ -326,11 +243,12 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t261.pci_offset;
ulong data = le32_to_cpu(ent->t261.write_data);
ql_dbg(ql_dbg_misc, vha, 0xd205,
"%s: wrpci [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
return qla27xx_next_entry(ent);
}
@@ -339,51 +257,50 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
uint area = ent->t262.ram_area;
ulong start = le32_to_cpu(ent->t262.start_addr);
ulong end = le32_to_cpu(ent->t262.end_addr);
ulong dwords;
ulong start;
ulong end;
ql_dbg(ql_dbg_misc, vha, 0xd206,
"%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
start = ent->t262.start_addr;
end = ent->t262.end_addr;
if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
if (area == T262_RAM_AREA_CRITICAL_RAM) {
;
} else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
} else if (area == T262_RAM_AREA_EXTERNAL_RAM) {
end = vha->hw->fw_memory_size;
if (buf)
ent->t262.end_addr = end;
} else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
ent->t262.end_addr = cpu_to_le32(end);
} else if (area == T262_RAM_AREA_SHARED_RAM) {
start = vha->hw->fw_shared_ram_start;
end = vha->hw->fw_shared_ram_end;
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
} else if (area == T262_RAM_AREA_DDR_RAM) {
start = vha->hw->fw_ddr_ram_start;
end = vha->hw->fw_ddr_ram_end;
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else if (ent->t262.ram_area == T262_RAM_AREA_MISC) {
} else if (area == T262_RAM_AREA_MISC) {
if (buf) {
ent->t262.start_addr = start;
ent->t262.end_addr = end;
ent->t262.start_addr = cpu_to_le32(start);
ent->t262.end_addr = cpu_to_le32(end);
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd022,
"%s: unknown area %x\n", __func__, ent->t262.ram_area);
"%s: unknown area %x\n", __func__, area);
qla27xx_skip_entry(ent, buf);
goto done;
}
if (end < start || start == 0 || end == 0) {
ql_dbg(ql_dbg_misc, vha, 0xd023,
"%s: unusable range (start=%x end=%x)\n", __func__,
ent->t262.end_addr, ent->t262.start_addr);
"%s: unusable range (start=%lx end=%lx)\n",
__func__, start, end);
qla27xx_skip_entry(ent, buf);
goto done;
}
@@ -402,13 +319,14 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
uint type = ent->t263.queue_type;
uint count = 0;
uint i;
uint length;
ql_dbg(ql_dbg_misc, vha, 0xd207,
"%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd207,
"%s: getq(%x) [%lx]\n", __func__, type, *len);
if (type == T263_QUEUE_TYPE_REQ) {
for (i = 0; i < vha->hw->max_req_queues; i++) {
struct req_que *req = vha->hw->req_q_map[i];
@@ -422,7 +340,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
count++;
}
}
} else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
} else if (type == T263_QUEUE_TYPE_RSP) {
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
@@ -450,7 +368,7 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd026,
"%s: unknown queue %x\n", __func__, ent->t263.queue_type);
"%s: unknown queue %x\n", __func__, type);
qla27xx_skip_entry(ent, buf);
}
@@ -496,12 +414,10 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ql_dbg(ql_dbg_misc, vha, 0xd209,
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd209,
"%s: pause risc [%lx]\n", __func__, *len);
if (buf)
qla24xx_pause_risc(reg, vha->hw);
qla24xx_pause_risc(ISPREG(vha), vha->hw);
return qla27xx_next_entry(ent);
}
@@ -522,11 +438,12 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
uint offset = ent->t267.pci_offset;
ulong data = le32_to_cpu(ent->t267.data);
ql_dbg(ql_dbg_misc, vha, 0xd20b,
"%s: dis intr [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
qla27xx_write_reg(ISPREG(vha), offset, data, buf);
return qla27xx_next_entry(ent);
}
@@ -622,17 +539,16 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong dwords = ent->t270.count;
ulong addr = ent->t270.addr;
ulong addr = le32_to_cpu(ent->t270.addr);
ulong dwords = le32_to_cpu(ent->t270.count);
ql_dbg(ql_dbg_misc, vha, 0xd20e,
"%s: rdremreg [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
qla27xx_write_reg(ISPREG(vha), IOBASE_ADDR, 0x40, buf);
while (dwords--) {
qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
qla27xx_write_reg(ISPREG(vha), 0xc0, addr|0x80000000, buf);
qla27xx_insert32(addr, buf, len);
qla27xx_read_reg(reg, 0xc4, buf, len);
qla27xx_read_reg(ISPREG(vha), 0xc4, buf, len);
addr += sizeof(uint32_t);
}
@@ -643,15 +559,14 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong addr = ent->t271.addr;
ulong data = ent->t271.data;
ulong addr = le32_to_cpu(ent->t271.addr);
ulong data = le32_to_cpu(ent->t271.data);
ql_dbg(ql_dbg_misc, vha, 0xd20f,
"%s: wrremreg [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
qla27xx_write_reg(reg, 0xc4, data, buf);
qla27xx_write_reg(reg, 0xc0, addr, buf);
qla27xx_write_reg(ISPREG(vha), IOBASE(vha), 0x40, buf);
qla27xx_write_reg(ISPREG(vha), 0xc4, data, buf);
qla27xx_write_reg(ISPREG(vha), 0xc0, addr, buf);
return qla27xx_next_entry(ent);
}
@@ -660,8 +575,8 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong dwords = ent->t272.count;
ulong start = ent->t272.addr;
ulong dwords = le32_to_cpu(ent->t272.count);
ulong start = le32_to_cpu(ent->t272.addr);
ql_dbg(ql_dbg_misc, vha, 0xd210,
"%s: rdremram [%lx]\n", __func__, *len);
@@ -680,8 +595,8 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong dwords = ent->t273.count;
ulong addr = ent->t273.addr;
ulong dwords = le32_to_cpu(ent->t273.count);
ulong addr = le32_to_cpu(ent->t273.addr);
uint32_t value;
ql_dbg(ql_dbg_misc, vha, 0xd211,
@@ -703,12 +618,13 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong type = ent->t274.queue_type;
uint count = 0;
uint i;
ql_dbg(ql_dbg_misc, vha, 0xd212,
"%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd212,
"%s: getqsh(%lx) [%lx]\n", __func__, type, *len);
if (type == T274_QUEUE_TYPE_REQ_SHAD) {
for (i = 0; i < vha->hw->max_req_queues; i++) {
struct req_que *req = vha->hw->req_q_map[i];
@@ -720,7 +636,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
count++;
}
}
} else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
} else if (type == T274_QUEUE_TYPE_RSP_SHAD) {
for (i = 0; i < vha->hw->max_rsp_queues; i++) {
struct rsp_que *rsp = vha->hw->rsp_q_map[i];
@@ -746,7 +662,7 @@ qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
}
} else {
ql_dbg(ql_dbg_misc, vha, 0xd02f,
"%s: unknown queue %x\n", __func__, ent->t274.queue_type);
"%s: unknown queue %lx\n", __func__, type);
qla27xx_skip_entry(ent, buf);
}
@@ -765,23 +681,26 @@ qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong offset = offsetof(typeof(*ent), t275.buffer);
ulong length = le32_to_cpu(ent->t275.length);
ulong size = le32_to_cpu(ent->hdr.size);
void *buffer = ent->t275.buffer;
ql_dbg(ql_dbg_misc, vha, 0xd213,
"%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
if (!ent->t275.length) {
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd213,
"%s: buffer(%lx) [%lx]\n", __func__, length, *len);
if (!length) {
ql_dbg(ql_dbg_misc, vha, 0xd020,
"%s: buffer zero length\n", __func__);
qla27xx_skip_entry(ent, buf);
goto done;
}
if (offset + ent->t275.length > ent->hdr.size) {
if (offset + length > size) {
length = size - offset;
ql_dbg(ql_dbg_misc, vha, 0xd030,
"%s: buffer overflow\n", __func__);
qla27xx_skip_entry(ent, buf);
goto done;
"%s: buffer overflow, truncate [%lx]\n", __func__, length);
ent->t275.length = cpu_to_le32(length);
}
qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
qla27xx_insertbuf(buffer, length, buf, len);
done:
return qla27xx_next_entry(ent);
}
@@ -790,15 +709,22 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t276(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
uint type = vha->hw->pdev->device >> 4 & 0xf;
uint func = vha->hw->port_no & 0x3;
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd214,
"%s: cond [%lx]\n", __func__, *len);
if (type != ent->t276.cond1 || func != ent->t276.cond2) {
ent = qla27xx_next_entry(ent);
qla27xx_skip_entry(ent, buf);
if (buf) {
ulong cond1 = le32_to_cpu(ent->t276.cond1);
ulong cond2 = le32_to_cpu(ent->t276.cond2);
uint type = vha->hw->pdev->device >> 4 & 0xf;
uint func = vha->hw->port_no & 0x3;
if (type != cond1 || func != cond2) {
struct qla27xx_fwdt_template *tmp = buf;
tmp->count--;
ent = qla27xx_next_entry(ent);
qla27xx_skip_entry(ent, buf);
}
}
return qla27xx_next_entry(ent);
@@ -808,13 +734,15 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t277(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong cmd_addr = le32_to_cpu(ent->t277.cmd_addr);
ulong wr_cmd_data = le32_to_cpu(ent->t277.wr_cmd_data);
ulong data_addr = le32_to_cpu(ent->t277.data_addr);
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd215,
"%s: rdpep [%lx]\n", __func__, *len);
qla27xx_insert32(ent->t277.wr_cmd_data, buf, len);
qla27xx_write_reg(reg, ent->t277.cmd_addr, ent->t277.wr_cmd_data, buf);
qla27xx_read_reg(reg, ent->t277.data_addr, buf, len);
qla27xx_insert32(wr_cmd_data, buf, len);
qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
qla27xx_read_reg(ISPREG(vha), data_addr, buf, len);
return qla27xx_next_entry(ent);
}
@@ -823,12 +751,15 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_t278(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
ulong cmd_addr = le32_to_cpu(ent->t278.cmd_addr);
ulong wr_cmd_data = le32_to_cpu(ent->t278.wr_cmd_data);
ulong data_addr = le32_to_cpu(ent->t278.data_addr);
ulong wr_data = le32_to_cpu(ent->t278.wr_data);
ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd216,
"%s: wrpep [%lx]\n", __func__, *len);
qla27xx_write_reg(reg, ent->t278.data_addr, ent->t278.wr_data, buf);
qla27xx_write_reg(reg, ent->t278.cmd_addr, ent->t278.wr_cmd_data, buf);
qla27xx_write_reg(ISPREG(vha), data_addr, wr_data, buf);
qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
return qla27xx_next_entry(ent);
}
@@ -837,8 +768,10 @@ static struct qla27xx_fwdt_entry *
qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
{
ulong type = le32_to_cpu(ent->hdr.type);
ql_dbg(ql_dbg_misc, vha, 0xd2ff,
"%s: type %x [%lx]\n", __func__, ent->hdr.type, *len);
"%s: other %lx [%lx]\n", __func__, type, *len);
qla27xx_skip_entry(ent, buf);
return qla27xx_next_entry(ent);
@@ -893,36 +826,27 @@ static void
qla27xx_walk_template(struct scsi_qla_host *vha,
struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
{
struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
ulong count = tmp->entry_count;
struct qla27xx_fwdt_entry *ent = (void *)tmp +
le32_to_cpu(tmp->entry_offset);
ulong type;
tmp->count = le32_to_cpu(tmp->entry_count);
ql_dbg(ql_dbg_misc, vha, 0xd01a,
"%s: entry count %lx\n", __func__, count);
while (count--) {
ent = qla27xx_find_entry(ent->hdr.type)(vha, ent, buf, len);
"%s: entry count %u\n", __func__, tmp->count);
while (ent && tmp->count--) {
type = le32_to_cpu(ent->hdr.type);
ent = qla27xx_find_entry(type)(vha, ent, buf, len);
if (!ent)
break;
}
if (count)
if (tmp->count)
ql_dbg(ql_dbg_misc, vha, 0xd018,
"%s: entry residual count (%lx)\n", __func__, count);
"%s: entry count residual=+%u\n", __func__, tmp->count);
if (ent)
ql_dbg(ql_dbg_misc, vha, 0xd019,
"%s: missing end entry (%lx)\n", __func__, count);
if (buf && *len != vha->hw->fw_dump_len)
ql_dbg(ql_dbg_misc, vha, 0xd01b,
"%s: length=%#lx residual=%+ld\n",
__func__, *len, vha->hw->fw_dump_len - *len);
if (buf) {
ql_log(ql_log_warn, vha, 0xd015,
"Firmware dump saved to temp buffer (%lu/%p)\n",
vha->host_no, vha->hw->fw_dump);
qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
}
"%s: missing end entry\n", __func__);
}
static void
@@ -945,8 +869,8 @@ qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
}
static void
qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
struct scsi_qla_host *vha)
qla27xx_firmware_info(struct scsi_qla_host *vha,
struct qla27xx_fwdt_template *tmp)
{
tmp->firmware_version[0] = vha->hw->fw_major_version;
tmp->firmware_version[1] = vha->hw->fw_minor_version;
@@ -963,19 +887,19 @@ ql27xx_edit_template(struct scsi_qla_host *vha,
{
qla27xx_time_stamp(tmp);
qla27xx_driver_info(tmp);
qla27xx_firmware_info(tmp, vha);
qla27xx_firmware_info(vha, tmp);
}
static inline uint32_t
qla27xx_template_checksum(void *p, ulong size)
{
uint32_t *buf = p;
__le32 *buf = p;
uint64_t sum = 0;
size /= sizeof(*buf);
while (size--)
sum += *buf++;
for ( ; size--; buf++)
sum += le32_to_cpu(*buf);
sum = (sum & 0xffffffff) + (sum >> 32);
@@ -991,29 +915,29 @@ qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
static inline int
qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
{
return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
return le32_to_cpu(tmp->template_type) == TEMPLATE_TYPE_FWDUMP;
}
static void
qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
static ulong
qla27xx_execute_fwdt_template(struct scsi_qla_host *vha,
struct qla27xx_fwdt_template *tmp, void *buf)
{
struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
ulong len;
ulong len = 0;
if (qla27xx_fwdt_template_valid(tmp)) {
len = tmp->template_size;
tmp = memcpy(vha->hw->fw_dump, tmp, len);
tmp = memcpy(buf, tmp, len);
ql27xx_edit_template(vha, tmp);
qla27xx_walk_template(vha, tmp, tmp, &len);
vha->hw->fw_dump_len = len;
vha->hw->fw_dumped = 1;
qla27xx_walk_template(vha, tmp, buf, &len);
}
return len;
}
ulong
qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha, void *p)
{
struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
struct qla27xx_fwdt_template *tmp = p;
ulong len = 0;
if (qla27xx_fwdt_template_valid(tmp)) {
@@ -1032,18 +956,6 @@ qla27xx_fwdt_template_size(void *p)
return tmp->template_size;
}
ulong
qla27xx_fwdt_template_default_size(void)
{
return sizeof(ql27xx_fwdt_default_template);
}
const void *
qla27xx_fwdt_template_default(void)
{
return ql27xx_fwdt_default_template;
}
int
qla27xx_fwdt_template_valid(void *p)
{
@@ -1051,7 +963,8 @@ qla27xx_fwdt_template_valid(void *p)
if (!qla27xx_verify_template_header(tmp)) {
ql_log(ql_log_warn, NULL, 0xd01c,
"%s: template type %x\n", __func__, tmp->template_type);
"%s: template type %x\n", __func__,
le32_to_cpu(tmp->template_type));
return false;
}
@@ -1074,17 +987,41 @@ qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
spin_lock_irqsave(&vha->hw->hardware_lock, flags);
#endif
if (!vha->hw->fw_dump)
ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
else if (!vha->hw->fw_dump_template)
ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
else if (vha->hw->fw_dumped)
ql_log(ql_log_warn, vha, 0xd300,
"Firmware has been previously dumped (%p),"
" -- ignoring request\n", vha->hw->fw_dump);
else {
QLA_FW_STOPPED(vha->hw);
qla27xx_execute_fwdt_template(vha);
if (!vha->hw->fw_dump) {
ql_log(ql_log_warn, vha, 0xd01e, "-> fwdump no buffer\n");
} else if (vha->hw->fw_dumped) {
ql_log(ql_log_warn, vha, 0xd01f,
"-> Firmware already dumped (%p) -- ignoring request\n",
vha->hw->fw_dump);
} else {
struct fwdt *fwdt = vha->hw->fwdt;
uint j;
ulong len;
void *buf = vha->hw->fw_dump;
for (j = 0; j < 2; j++, fwdt++, buf += len) {
ql_log(ql_log_warn, vha, 0xd011,
"-> fwdt%u running...\n", j);
if (!fwdt->template) {
ql_log(ql_log_warn, vha, 0xd012,
"-> fwdt%u no template\n", j);
break;
}
len = qla27xx_execute_fwdt_template(vha,
fwdt->template, buf);
if (len != fwdt->dump_size) {
ql_log(ql_log_warn, vha, 0xd013,
"-> fwdt%u fwdump residual=%+ld\n",
j, fwdt->dump_size - len);
}
}
vha->hw->fw_dump_len = buf - (void *)vha->hw->fw_dump;
vha->hw->fw_dumped = 1;
ql_log(ql_log_warn, vha, 0xd015,
"-> Firmware dump saved to buffer (%lu/%p) <%lx>\n",
vha->host_no, vha->hw->fw_dump, vha->hw->fw_dump_cap_flags);
qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
}
#ifndef __CHECKER__
qla2x00t-32gbit/qla_tmpl.h
+38 -38
View File
@@ -11,12 +11,12 @@
#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
struct __packed qla27xx_fwdt_template {
uint32_t template_type;
uint32_t entry_offset;
__le32 template_type;
__le32 entry_offset;
uint32_t template_size;
uint32_t reserved_1;
uint32_t count; /* borrow field for running/residual count */
uint32_t entry_count;
__le32 entry_count;
uint32_t template_version;
uint32_t capture_timestamp;
uint32_t template_checksum;
@@ -65,8 +65,8 @@ struct __packed qla27xx_fwdt_template {
struct __packed qla27xx_fwdt_entry {
struct __packed {
uint32_t type;
uint32_t size;
__le32 type;
__le32 size;
uint32_t reserved_1;
uint8_t capture_flags;
@@ -81,36 +81,36 @@ struct __packed qla27xx_fwdt_entry {
} t255;
struct __packed {
uint32_t base_addr;
__le32 base_addr;
uint8_t reg_width;
uint16_t reg_count;
__le16 reg_count;
uint8_t pci_offset;
} t256;
struct __packed {
uint32_t base_addr;
uint32_t write_data;
__le32 base_addr;
__le32 write_data;
uint8_t pci_offset;
uint8_t reserved[3];
} t257;
struct __packed {
uint32_t base_addr;
__le32 base_addr;
uint8_t reg_width;
uint16_t reg_count;
__le16 reg_count;
uint8_t pci_offset;
uint8_t banksel_offset;
uint8_t reserved[3];
uint32_t bank;
__le32 bank;
} t258;
struct __packed {
uint32_t base_addr;
uint32_t write_data;
__le32 base_addr;
__le32 write_data;
uint8_t reserved[2];
uint8_t pci_offset;
uint8_t banksel_offset;
uint32_t bank;
__le32 bank;
} t259;
struct __packed {
@@ -121,14 +121,14 @@ struct __packed qla27xx_fwdt_entry {
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
uint32_t write_data;
__le32 write_data;
} t261;
struct __packed {
uint8_t ram_area;
uint8_t reserved[3];
uint32_t start_addr;
uint32_t end_addr;
__le32 start_addr;
__le32 end_addr;
} t262;
struct __packed {
@@ -158,7 +158,7 @@ struct __packed qla27xx_fwdt_entry {
struct __packed {
uint8_t pci_offset;
uint8_t reserved[3];
uint32_t data;
__le32 data;
} t267;
struct __packed {
@@ -173,23 +173,23 @@ struct __packed qla27xx_fwdt_entry {
} t269;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t270;
struct __packed {
uint32_t addr;
uint32_t data;
__le32 addr;
__le32 data;
} t271;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t272;
struct __packed {
uint32_t addr;
uint32_t count;
__le32 addr;
__le32 count;
} t273;
struct __packed {
@@ -199,26 +199,26 @@ struct __packed qla27xx_fwdt_entry {
} t274;
struct __packed {
uint32_t length;
__le32 length;
uint8_t buffer[];
} t275;
struct __packed {
uint32_t cond1;
uint32_t cond2;
__le32 cond1;
__le32 cond2;
} t276;
struct __packed {
uint32_t cmd_addr;
uint32_t wr_cmd_data;
uint32_t data_addr;
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
} t277;
struct __packed {
uint32_t cmd_addr;
uint32_t wr_cmd_data;
uint32_t data_addr;
uint32_t wr_data;
__le32 cmd_addr;
__le32 wr_cmd_data;
__le32 data_addr;
__le32 wr_data;
} t278;
};
};
qla2x00t-32gbit/qla_version.h
+2 -2
View File
@@ -7,9 +7,9 @@
/*
* Driver version
*/
#define QLA2XXX_VERSION "10.00.00.14-k"
#define QLA2XXX_VERSION "10.01.00.16-k"
#define QLA_DRIVER_MAJOR_VER 10
#define QLA_DRIVER_MINOR_VER 0
#define QLA_DRIVER_MINOR_VER 1
#define QLA_DRIVER_PATCH_VER 0
#define QLA_DRIVER_BETA_VER 0
scst/include/backport.h
+22 -3
View File
@@ -43,6 +43,7 @@
#include <scsi/scsi_cmnd.h> /* struct scsi_cmnd */
struct scsi_target;
#include <scsi/scsi_transport_fc.h> /* struct fc_bsg_job */
#include <asm/unaligned.h> /* get_unaligned_be64() */
/* <asm-generic/barrier.h> */
@@ -1544,13 +1545,30 @@ static inline void *vzalloc(unsigned long size)
#endif
/* <linux/wait.h> */
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)
/*
* See also commit 35a2af94c7ce ("sched/wait: Make the __wait_event*()
* interface more friendly") # v3.13.
*/
#define ___wait_cond_timeout_backport(condition)\
({ \
bool __cond = (condition); \
if (__cond && !__ret) \
__ret = 1; \
__cond || !__ret; \
})
#elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
#define ___wait_cond_timeout_backport ___wait_cond_timeout
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
/*
* See also commit 25ab0bc334b4 ("scsi: sched/wait: Add
* wait_event_lock_irq_timeout for TASK_UNINTERRUPTIBLE usage") # v4.20.
*/
#define __wait_event_lock_irq_timeout(wq_head, condition, lock, timeout, state)\
___wait_event(wq_head, ___wait_cond_timeout(condition), \
___wait_event(wq_head, ___wait_cond_timeout_backport(condition),\
state, 0, timeout, \
spin_unlock_irq(&lock); \
__ret = schedule_timeout(__ret); \
@@ -1559,7 +1577,7 @@ static inline void *vzalloc(unsigned long size)
#define wait_event_lock_irq_timeout(wq_head, condition, lock, timeout) \
({ \
long __ret = timeout; \
if (!___wait_cond_timeout(condition)) \
if (!___wait_cond_timeout_backport(condition)) \
__ret = __wait_event_lock_irq_timeout( \
wq_head, condition, lock, timeout,\
TASK_UNINTERRUPTIBLE); \
@@ -1639,7 +1657,8 @@ enum {
};
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0) && \
(!defined(RHEL_MAJOR) || RHEL_MAJOR -0 < 7)
/*
* See also commit cc019a5a3b58 ("scsi: scsi_transport_fc: fix typos on 64/128
* GBit define names") # v4.16.