mirror of
https://github.com/SCST-project/scst.git
synced 2026-05-20 20:21:30 +00:00
mvsas_tgt: Fix sparse warnings
Also, remove unused variables, data structures and functions. git-svn-id: http://svn.code.sf.net/p/scst/svn/trunk@5215 d57e44dd-8a1f-0410-8b47-8ef2f437770f
This commit is contained in:
@@ -553,11 +553,12 @@ static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
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return MVS_ID_NOT_MAPPED;
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}
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void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
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static void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
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{
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int i;
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struct scatterlist *sg;
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struct mvs_prd *buf_prd = prd;
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for_each_sg(scatter, sg, nr, i) {
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buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
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buf_prd->len = cpu_to_le32(sg_dma_len(sg));
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@@ -624,8 +625,8 @@ static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
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mvs_write_port_vsr_data(mvi, i, tmp);
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}
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void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates)
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static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates)
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{
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u32 lrmin = 0, lrmax = 0;
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u32 tmp;
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@@ -713,26 +714,23 @@ static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
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}
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u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
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static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs_ex;
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return ior32(SPI_DATA_REG_64XX);
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}
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void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
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static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
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{
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void __iomem *regs = mvi->regs_ex;
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iow32(SPI_DATA_REG_64XX, data);
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iow32(SPI_DATA_REG_64XX, data);
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}
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int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
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u32 *dwCmd,
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u8 cmd,
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u8 read,
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u8 length,
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u32 addr
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)
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static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi, u32 *dwCmd, u8 cmd,
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u8 read, u8 length, u32 addr)
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{
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u32 dwTmp;
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@@ -750,7 +748,7 @@ int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
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}
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int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
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static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
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{
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void __iomem *regs = mvi->regs_ex;
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int retry;
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@@ -765,7 +763,7 @@ int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
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return 0;
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}
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int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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{
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void __iomem *regs = mvi->regs_ex;
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u32 i, dwTmp;
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@@ -781,7 +779,8 @@ int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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}
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#ifndef DISABLE_HOTPLUG_DMA_FIX
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void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
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static void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from,
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void *prd)
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{
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int i;
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struct mvs_prd *buf_prd = prd;
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@@ -599,8 +599,8 @@ static void mvs_94xx_phy_work_around(struct mvs_info *mvi, int i)
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mvs_write_port_vsr_data(mvi, i, tmp);
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}
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void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates)
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static void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates)
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{
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u32 lrmax = 0;
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u32 tmp;
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@@ -656,26 +656,23 @@ static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
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}
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u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
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static u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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return mr32(SPI_RD_DATA_REG_94XX);
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}
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void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
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static void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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mw32(SPI_RD_DATA_REG_94XX, data);
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mw32(SPI_RD_DATA_REG_94XX, data);
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}
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int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
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u32 *dwCmd,
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u8 cmd,
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u8 read,
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u8 length,
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u32 addr
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)
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static int mvs_94xx_spi_buildcmd(struct mvs_info *mvi, u32 *dwCmd, u8 cmd,
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u8 read, u8 length, u32 addr)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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u32 dwTmp;
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@@ -694,15 +691,16 @@ int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
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}
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int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
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static int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
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return 0;
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}
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int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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static int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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u32 i, dwTmp;
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@@ -718,7 +716,8 @@ int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
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}
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#ifndef DISABLE_HOTPLUG_DMA_FIX
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void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
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static void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from,
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void *prd)
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{
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int i;
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struct mvs_prd *buf_prd = prd;
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@@ -44,9 +44,9 @@ static const struct mvs_chip_info mvs_chips[] = {
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struct mvs_info *tgt_mvi;
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struct mvs_tgt_initiator mvs_tgt;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)
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struct class_device_attribute *mvst_host_attrs[];
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static struct class_device_attribute *mvst_host_attrs[];
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#else
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struct device_attribute *mvst_host_attrs[];
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static struct device_attribute *mvst_host_attrs[];
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#endif
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#endif
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@@ -241,7 +241,7 @@ static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
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unsigned long buf_size;
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void *buf;
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dma_addr_t buf_dma;
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struct mvs_slot_info *slot = 0;
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struct mvs_slot_info *slot = NULL;
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if (mvi->flags & MVF_FLAG_SOC)
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slot_nr = MVS_SOC_SLOTS;
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@@ -350,7 +350,7 @@ int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
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mvi->regs_ex = ioremap_nocache(res_start,
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res_len);
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} else
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mvi->regs_ex = (void *)res_start;
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mvi->regs_ex = (void __iomem *)res_start;
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if (!mvi->regs_ex)
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goto err_out;
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}
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@@ -972,7 +972,7 @@ static DEVICE_ATTR(target_mode,
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mvs_show_tgt_enabled,
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mvs_store_tgt_enabled);
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struct device_attribute *mvst_host_attrs[] = {
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static struct device_attribute *mvst_host_attrs[] = {
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&dev_attr_target_mode,
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NULL,
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};
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@@ -983,7 +983,6 @@ struct device_attribute *mvst_host_attrs[] = {
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/* task handler */
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struct task_struct *mvs_th;
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static int __init mvs_init(void)
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{
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int rc;
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@@ -206,7 +206,7 @@ void mvs_get_sas_addr(void *buf, u32 buflen)
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/*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
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}
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struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
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static struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
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{
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unsigned long i = 0, j = 0, hi = 0;
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struct sas_ha_struct *sha = dev->port->ha;
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@@ -235,7 +235,7 @@ struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
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}
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/* FIXME */
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int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
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static int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
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{
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unsigned long i = 0, j = 0, n = 0, num = 0;
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struct mvs_device *mvi_dev = dev->lldd_dev;
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@@ -1337,7 +1337,7 @@ void mvs_port_deformed(struct asd_sas_phy *sas_phy)
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mvs_port_notify_deformed(sas_phy, 1);
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}
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struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
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static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
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{
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u32 dev;
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for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
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@@ -1354,7 +1354,7 @@ struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
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return NULL;
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}
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void mvs_free_dev(struct mvs_device *mvi_dev)
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static void mvs_free_dev(struct mvs_device *mvi_dev)
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{
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u32 id = mvi_dev->device_id;
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memset(mvi_dev, 0, sizeof(*mvi_dev));
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@@ -1364,7 +1364,7 @@ void mvs_free_dev(struct mvs_device *mvi_dev)
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mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
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}
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int mvs_dev_found_notify(struct domain_device *dev, int lock)
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static int mvs_dev_found_notify(struct domain_device *dev, int lock)
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{
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unsigned long flags = 0;
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int res = 0;
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@@ -1418,7 +1418,7 @@ int mvs_dev_found(struct domain_device *dev)
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return mvs_dev_found_notify(dev, 1);
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}
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void mvs_dev_gone_notify(struct domain_device *dev)
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static void mvs_dev_gone_notify(struct domain_device *dev)
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{
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unsigned long flags = 0;
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struct mvs_device *mvi_dev = dev->lldd_dev;
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@@ -1861,6 +1861,8 @@ static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
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int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
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__releases(&mvi->lock)
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__acquires(&mvi->lock)
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{
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u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
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struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
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@@ -35,74 +35,31 @@ u8 DEFAULT_SPI_CMD[16] =
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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};
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#else
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u8 ATMEL_SPI_CMD[16] =
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static u8 ATMEL_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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};
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u8 MXIC_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0x60, 0x90
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};
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u8 WINBOND_SPI_CMD[16] =
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static u8 WINBOND_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0xC7, 0xAB
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};
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u8 ATMEL_SPI_CMD_41a_021[16] =
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static u8 ATMEL_SPI_CMD_41a_021[16] =
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{
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/* 0 1 2 3 4 5 6 7 8 9 10 11*/
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0xD8, 0x60, 0x9F, 0x36, 0x39, 0x3C
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};
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u8 EON_F20_SPI_CMD[16] =
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static u8 EON_F20_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0x60, 0x90
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};
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#endif
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int spi_rdsr(struct mvs_info *mvi, u8 *sr)
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{
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u32 dwTmp;
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MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
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(u8)SPICmd[SPI_INS_RDSR],
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1,
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1,
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-1);
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MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
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if (0 == MVS_CHIP_DISP->spi_waitdataready(mvi, 10000)) {
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dwTmp = MVS_CHIP_DISP->spi_read_data(mvi);
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*sr = (u8)dwTmp;
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return 0;
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} else {
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mv_dprintk("timeout\n");
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}
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return -1;
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}
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int spi_pollisr(struct mvs_info *mvi, u8 mask, u8 bit, u32 timeout)
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{
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u32 i;
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u8 sr;
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for (i = 0; i < timeout; i++) {
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if (0 == spi_rdsr(mvi, &sr)) {
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if ((sr & mask) == bit)
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return 0;
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}
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msleep(20);
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}
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return -1;
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}
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#ifdef IDENTIFY_SPI
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#define SPI_IDENTIFY_TIMER 10000
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int spi_atmelidentify(struct mvs_info *mvi)
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static int spi_atmelidentify(struct mvs_info *mvi)
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{
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u32 dwtmp;
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MVS_CHIP_DISP->spi_buildcmd(mvi, &dwtmp,
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@@ -125,7 +82,7 @@ int spi_atmelidentify(struct mvs_info *mvi)
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return -1;
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}
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int spi_atmelidentify_41a_021(struct mvs_info *mvi)
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static int spi_atmelidentify_41a_021(struct mvs_info *mvi)
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{
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u32 dwTmp;
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MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
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@@ -155,7 +112,7 @@ int spi_atmelidentify_41a_021(struct mvs_info *mvi)
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}
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int spi_winbondidentify(struct mvs_info *mvi)
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static int spi_winbondidentify(struct mvs_info *mvi)
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{
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u32 dwTmp;
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@@ -180,31 +137,7 @@ int spi_winbondidentify(struct mvs_info *mvi)
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return -1;
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}
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int spi_mxicidentify(struct mvs_info *mvi)
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{
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u32 dwTmp;
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MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
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MXIC_SPI_CMD[SPI_INS_RDID],
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1,
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2,
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0);
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MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
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if (0 == MVS_CHIP_DISP->spi_waitdataready(mvi, SPI_IDENTIFY_TIMER)) {
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dwTmp = MVS_CHIP_DISP->spi_read_data(mvi);
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switch (dwTmp) {
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case 0x11C2:
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mvi->flashid = MX25L2005;
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mvi->flashsize = 256L * 1024;
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mvi->flashsectSize = 4L * 1024;
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return 0;
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}
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}
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return -1;
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}
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int spi_eonidentify_f20(struct mvs_info *mvi)
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static int spi_eonidentify_f20(struct mvs_info *mvi)
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{
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u32 dwTmp;
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@@ -232,7 +165,7 @@ int spi_eonidentify_f20(struct mvs_info *mvi)
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#endif
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int spi_init(struct mvs_info *mvi)
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static int spi_init(struct mvs_info *mvi)
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{
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u32 i;
|
||||
#ifndef IDENTIFY_SPI
|
||||
@@ -270,7 +203,7 @@ int spi_init(struct mvs_info *mvi)
|
||||
#endif
|
||||
}
|
||||
|
||||
int spi_read(struct mvs_info *mvi, u32 addr, u8 *data, u8 size)
|
||||
static int spi_read(struct mvs_info *mvi, u32 addr, u8 *data, u8 size)
|
||||
{
|
||||
u32 i, dwTmp;
|
||||
|
||||
@@ -294,7 +227,7 @@ int spi_read(struct mvs_info *mvi, u32 addr, u8 *data, u8 size)
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_readbuf(struct mvs_info *mvi, u32 addr, u8 *data, u32 count)
|
||||
static int spi_readbuf(struct mvs_info *mvi, u32 addr, u8 *data, u32 count)
|
||||
{
|
||||
u32 i, j;
|
||||
u32 tmpAddr, tmpdata, addrend;
|
||||
@@ -325,7 +258,7 @@ int spi_readbuf(struct mvs_info *mvi, u32 addr, u8 *data, u32 count)
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 mvverifychecksum(u8 *address, u32 Size)
|
||||
static u8 mvverifychecksum(u8 *address, u32 Size)
|
||||
{
|
||||
u8 checkSum = 0;
|
||||
u32 temp = 0;
|
||||
@@ -336,149 +269,8 @@ u8 mvverifychecksum(u8 *address, u32 Size)
|
||||
return checkSum;
|
||||
}
|
||||
|
||||
u8 mvcalculatechecksum(u8 *address, u32 size)
|
||||
{
|
||||
u8 checkSum;
|
||||
u32 temp = 0;
|
||||
checkSum = 0;
|
||||
|
||||
for (temp = 0; temp < size; temp++)
|
||||
checkSum += address[temp];
|
||||
|
||||
checkSum = (~checkSum) + 1;
|
||||
return checkSum;
|
||||
}
|
||||
|
||||
int spi_wren(struct mvs_info *mvi)
|
||||
{
|
||||
u32 dwTmp;
|
||||
|
||||
MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
|
||||
(u8)SPICmd[SPI_INS_WREN],
|
||||
0,
|
||||
0,
|
||||
-1);
|
||||
MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
|
||||
|
||||
if (0 != MVS_CHIP_DISP->spi_waitdataready(mvi, 10000))
|
||||
return -1;
|
||||
if (0 == spi_pollisr(mvi, 0x03, 0x02, 300000))
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_rdpt(struct mvs_info *mvi, u32 addr, u8 *data)
|
||||
{
|
||||
u32 dwTmp;
|
||||
|
||||
MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
|
||||
(u8)SPICmd[SPI_INS_RDPT],
|
||||
1,
|
||||
1,
|
||||
addr);
|
||||
MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
|
||||
|
||||
if (0 == MVS_CHIP_DISP->spi_waitdataready(mvi, 10000)) {
|
||||
dwTmp = MVS_CHIP_DISP->spi_read_data(mvi);
|
||||
*data = (u8)dwTmp;
|
||||
return 0;
|
||||
} else {
|
||||
mv_dprintk("SPI_RDPT timeout\n");
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_sectunprotect(struct mvs_info *mvi, u32 addr)
|
||||
{
|
||||
u32 dwTmp;
|
||||
u8 protect_sect = 0xFF;
|
||||
if (-1 == spi_rdpt(mvi, addr, &protect_sect))
|
||||
return -1;
|
||||
|
||||
if (protect_sect == 0)
|
||||
return 0;
|
||||
|
||||
if (-1 == spi_wren(mvi))
|
||||
return -1;
|
||||
|
||||
MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
|
||||
(u8)SPICmd[SPI_INS_UPTSEC],
|
||||
0,
|
||||
0,
|
||||
addr);
|
||||
MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
|
||||
if (0 != MVS_CHIP_DISP->spi_waitdataready(mvi, 10000))
|
||||
return -1;
|
||||
if (0 == spi_pollisr(mvi, 0x03, 0, 300000))
|
||||
return 0;
|
||||
mv_dprintk("error SPI_SectUnprotect \n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_secterase(struct mvs_info *mvi, u32 addr)
|
||||
{
|
||||
u32 dwTmp;
|
||||
|
||||
if (-1 == spi_wren(mvi))
|
||||
return -1;
|
||||
|
||||
if ((mvi->flashid == AT25DF041A) || (mvi->flashid == AT25DF021)) {
|
||||
if (-1 == spi_sectunprotect(mvi, addr)) {
|
||||
mv_dprintk("Un protect error.\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
|
||||
(u8)SPICmd[SPI_INS_SERASE],
|
||||
0,
|
||||
0,
|
||||
addr);
|
||||
MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
|
||||
if (0 != MVS_CHIP_DISP->spi_waitdataready(mvi, 10000))
|
||||
return -1;
|
||||
if (0 == spi_pollisr(mvi, 0x03, 0, 300000))
|
||||
return 0;
|
||||
mv_dprintk("error SPI_SectErase\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_write(struct mvs_info *mvi, u32 addr, u32 data)
|
||||
{
|
||||
u32 dwTmp;
|
||||
|
||||
spi_wren(mvi);
|
||||
MVS_CHIP_DISP->spi_write_data(mvi, data);
|
||||
MVS_CHIP_DISP->spi_buildcmd(mvi, &dwTmp,
|
||||
(u8)SPICmd[SPI_INS_RPOG],
|
||||
0,
|
||||
4,
|
||||
addr);
|
||||
MVS_CHIP_DISP->spi_issuecmd(mvi, dwTmp);
|
||||
|
||||
if (0 != MVS_CHIP_DISP->spi_waitdataready(mvi, 10000)) {
|
||||
mv_dprintk("timeout\n");
|
||||
return -1;
|
||||
}
|
||||
if (0 == spi_pollisr(mvi, 0x01, 0, 5000))
|
||||
return 0;
|
||||
mv_dprintk("timeout\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
int spi_writebuf(struct mvs_info *mvi, u32 addr, u32 *data, u32 count)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < count; i += 4) {
|
||||
if (-1 == spi_write(mvi, addr + i, *(u32 *)&data[i])) {
|
||||
mv_dprintk("Write failed at %5.5x\n", addr+i);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool mvui_init_param(struct mvs_info *mvi, struct hba_info_main *hba_info_para)
|
||||
static bool mvui_init_param(struct mvs_info *mvi,
|
||||
struct hba_info_main *hba_info_para)
|
||||
{
|
||||
u32 param_flash_addr = PARA_OFF;
|
||||
if (!mvi)
|
||||
|
||||
@@ -68,10 +68,9 @@ static int mvst_start_sas_target(struct mvs_info *mvi, u8 id);
|
||||
static int mvst_restart_free_list(struct mvs_info *mvi, u8 slot_id);
|
||||
static uint16_t mvst_get_scsi_transport_version(struct scst_tgt *scst_tgt);
|
||||
|
||||
struct kmem_cache *mvst_cmd_cachep;
|
||||
struct mvst_msg_queue tgt_msg_queue;
|
||||
static struct kmem_cache *mvst_cmd_cachep;
|
||||
|
||||
struct scst_tgt_template tgt_template = {
|
||||
static struct scst_tgt_template tgt_template = {
|
||||
.name = MVST_NAME,
|
||||
.sg_tablesize = 0,
|
||||
.use_clustering = 1,
|
||||
@@ -134,30 +133,6 @@ mvst_prep_prd(struct mvst_prm *prm, struct mvs_prd *buf_prd)
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
mvst_fixup_payload(u32 *payload, u32 nr_pl_dwords)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
while (nr_pl_dwords--) {
|
||||
tmp = *payload;
|
||||
tmp = ((tmp & 0x000000FF) << 24) |
|
||||
((tmp & 0x0000FF00) << 8) |
|
||||
((tmp & 0x00FF0000) >> 8) |
|
||||
((tmp & 0xFF000000) >> 24);
|
||||
*payload = tmp;
|
||||
payload++;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
memory_dword_copy(u32 *dst, u32 *src, u32 nr_bytes)
|
||||
{
|
||||
nr_bytes /= sizeof(u32);
|
||||
while (nr_bytes--)
|
||||
*dst++ = *src++;
|
||||
}
|
||||
|
||||
static inline int test_tgt_sess_count(struct mvst_tgt *tgt,
|
||||
struct mvs_info *mvi)
|
||||
{
|
||||
@@ -523,7 +498,7 @@ static int mvst_prep_resp_frame(struct mvst_prm *prm,
|
||||
static int
|
||||
mvst_send_resp(struct mvs_info *mvi, struct mvst_cmd *cmd)
|
||||
{
|
||||
struct mvst_prm prm = { 0 };
|
||||
struct mvst_prm prm = { NULL };
|
||||
struct scst_cmd *scst_cmd = cmd->scst_cmd;
|
||||
u16 pass = 0;
|
||||
struct mvs_slot_info *slot;
|
||||
@@ -760,7 +735,7 @@ static int mvst_xmit_response(struct scst_cmd *scst_cmd)
|
||||
struct mvst_sess *sess;
|
||||
int is_send_status;
|
||||
unsigned long flags = 0;
|
||||
struct mvst_prm prm = { 0 };
|
||||
struct mvst_prm prm = { NULL };
|
||||
struct mvs_info *mvi;
|
||||
|
||||
TRACE_ENTRY();
|
||||
@@ -1038,7 +1013,7 @@ static int mvst_rdy_to_xfer(struct scst_cmd *scst_cmd)
|
||||
int res = SCST_TGT_RES_SUCCESS;
|
||||
struct mvst_sess *sess;
|
||||
unsigned long flags = 0;
|
||||
struct mvst_prm prm = { 0 };
|
||||
struct mvst_prm prm = { NULL };
|
||||
struct mvs_slot_info *slot;
|
||||
u32 rc = 0, pass = 0;
|
||||
struct mvs_info *mvi;
|
||||
@@ -1432,8 +1407,9 @@ out:
|
||||
|
||||
}
|
||||
|
||||
struct mvst_port *mvst_get_port_by_sasaddr(struct mvs_info *mvi,
|
||||
u64 dst_sas_addr, u64 src_sas_addr)
|
||||
static struct mvst_port *mvst_get_port_by_sasaddr(struct mvs_info *mvi,
|
||||
u64 dst_sas_addr,
|
||||
u64 src_sas_addr)
|
||||
{
|
||||
int n = 0;
|
||||
for (n = 0; n < mvi->chip->n_phy; n++) {
|
||||
@@ -1470,10 +1446,8 @@ struct mvst_port *mvst_get_port_by_sasaddr(struct mvs_info *mvi,
|
||||
return &mvi->tgt_port[n];
|
||||
}
|
||||
|
||||
int mvst_build_cmd(struct mvs_info *mvi,
|
||||
struct mvs_slot_info *slot,
|
||||
struct mvst_cmd **pcmd,
|
||||
int cmd_type)
|
||||
static int mvst_build_cmd(struct mvs_info *mvi, struct mvs_slot_info *slot,
|
||||
struct mvst_cmd **pcmd, int cmd_type)
|
||||
{
|
||||
int res = 0;
|
||||
u64 src_sas_addr, dst_sas_addr;
|
||||
@@ -1552,8 +1526,8 @@ out:
|
||||
|
||||
|
||||
/* mvi->lock supposed to be held on entry */
|
||||
int mvst_send_cmd_to_scst(struct mvs_info *mvi,
|
||||
struct mvs_slot_info *slot)
|
||||
static int mvst_send_cmd_to_scst(struct mvs_info *mvi,
|
||||
struct mvs_slot_info *slot)
|
||||
{
|
||||
int res = 0;
|
||||
u64 initiator_sas_addr;
|
||||
@@ -1868,7 +1842,7 @@ static inline int mvst_send_notify_ack(struct mvst_cmd *cmd, int status)
|
||||
int res = 0;
|
||||
u8 buf[4] = {0, 0, 0, 0};
|
||||
struct mvs_slot_info *resp_slot;
|
||||
struct mvst_prm prm = { 0 };
|
||||
struct mvst_prm prm = { NULL };
|
||||
struct mvs_info *mvi = cmd->sess->tgt->mvi;
|
||||
|
||||
TRACE_ENTRY();
|
||||
@@ -1935,7 +1909,7 @@ static int mvst_send_busy(struct mvs_info *mvi, struct mvs_slot_info *slot)
|
||||
int res = 0;
|
||||
struct mvs_slot_info *resp_slot;
|
||||
struct mvst_cmd *cmd = NULL;
|
||||
struct mvst_prm prm = { 0 };
|
||||
struct mvst_prm prm = { NULL };
|
||||
|
||||
TRACE_ENTRY();
|
||||
|
||||
@@ -2088,18 +2062,6 @@ out:
|
||||
return rc;
|
||||
}
|
||||
|
||||
void mvs_enable_taget_xmt(struct mvs_info *mvi, int PhyId)
|
||||
{
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 tmp;
|
||||
|
||||
tmp = mr32(MVS_PCS);
|
||||
#ifdef SUPPORT_TARGET
|
||||
tmp |= PCS_RSP_RX_EN;
|
||||
#endif
|
||||
mw32(MVS_PCS, tmp);
|
||||
}
|
||||
|
||||
static void mvst_register_tgt_handler(struct mvs_info *mvi)
|
||||
{
|
||||
struct mvst_tgt *tgt = NULL;
|
||||
@@ -2710,7 +2672,7 @@ out:
|
||||
return res;
|
||||
}
|
||||
|
||||
void mvs_tgt_unregister_driver(void)
|
||||
static void mvs_tgt_unregister_driver(void)
|
||||
{
|
||||
ENTER(__func__);
|
||||
memset(&mvs_tgt, 0, sizeof(mvs_tgt));
|
||||
@@ -2718,43 +2680,6 @@ void mvs_tgt_unregister_driver(void)
|
||||
return;
|
||||
}
|
||||
|
||||
void mvst_msg_insert(struct mvst_msg_queue *msg_queue,
|
||||
void *data, unsigned int event, u64 param)
|
||||
{
|
||||
struct mvst_msg *msg;
|
||||
unsigned long flags;
|
||||
|
||||
mv_dprintk("msg insert %d.\n", event);
|
||||
spin_lock_irqsave(&msg_queue->msg_lock, flags);
|
||||
if (list_empty(&msg_queue->free)) {
|
||||
/* should wreck some havoc ...*/
|
||||
PRINT_ERROR("%s :Message queue is full.", __func__);
|
||||
spin_unlock_irqrestore(&msg_queue->msg_lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
msg = list_entry(msg_queue->free.next, struct mvst_msg, msg_entry);
|
||||
msg->data = data;
|
||||
msg->msg = event;
|
||||
|
||||
switch (event) {
|
||||
case EVENT_DEVICE_REMOVAL:
|
||||
case EVENT_DEVICE_ARRIVAL:
|
||||
msg->param = param;
|
||||
break;
|
||||
default:
|
||||
msg->param = param;
|
||||
break;
|
||||
}
|
||||
|
||||
list_move_tail(&msg->msg_entry, &msg_queue->tasks);
|
||||
spin_unlock_irqrestore(&msg_queue->msg_lock, flags);
|
||||
|
||||
if (msg_queue->msg_task)
|
||||
wake_up_process(msg_queue->msg_task);
|
||||
}
|
||||
|
||||
|
||||
void mvst_init_tgt_port(struct mvs_info *mvi)
|
||||
{
|
||||
INIT_LIST_HEAD(&mvi->data_cmd_list);
|
||||
|
||||
Reference in New Issue
Block a user