mirror of
https://github.com/SCST-project/scst.git
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mvsas_tgt: Fix various checkpatch complaints, mainly about whitespace usage
git-svn-id: http://svn.code.sf.net/p/scst/svn/trunk@5216 d57e44dd-8a1f-0410-8b47-8ef2f437770f
This commit is contained in:
Bart Van Assche
+5
-5
@@ -136,13 +136,13 @@ struct mvs_prd {
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__le32 len; /* 16-bit length */
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};
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#define SPI_CTRL_REG 0xc0
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#define SPI_CTRL_REG 0xc0
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#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
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#define SPI_CTRL_SPIRDY (1U<<22)
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#define SPI_CTRL_SPISTART (1U<<20)
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#define SPI_CTRL_SPIRDY (1U<<22)
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#define SPI_CTRL_SPISTART (1U<<20)
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#define SPI_CMD_REG 0xc4
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#define SPI_DATA_REG 0xc8
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#define SPI_CMD_REG 0xc4
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#define SPI_DATA_REG 0xc8
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#define SPI_CTRL_REG_64XX 0x10
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#define SPI_CMD_REG_64XX 0x14
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+1
-1
@@ -258,7 +258,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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/* set phy int mask */
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tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
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PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
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PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR;
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mvs_write_port_irq_mask(mvi, i, tmp);
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msleep(100);
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+9
-9
@@ -96,8 +96,8 @@ enum hw_registers {
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MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
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/* phys 1-3 follow after this */
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/* multiplexing */
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MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
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MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
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MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
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MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
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MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
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MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
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};
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@@ -191,13 +191,13 @@ struct mvs_prd {
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__le32 im_len;
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} __attribute__ ((packed));
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#define SPI_CTRL_REG_94XX 0xc800
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#define SPI_ADDR_REG_94XX 0xc804
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#define SPI_WR_DATA_REG_94XX 0xc808
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#define SPI_RD_DATA_REG_94XX 0xc80c
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#define SPI_CTRL_READ_94XX (1U << 2)
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#define SPI_ADDR_VLD_94XX (1U << 1)
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#define SPI_CTRL_SpiStart_94XX (1U << 0)
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#define SPI_CTRL_REG_94XX 0xc800
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#define SPI_ADDR_REG_94XX 0xc804
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#define SPI_WR_DATA_REG_94XX 0xc808
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#define SPI_RD_DATA_REG_94XX 0xc80c
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#define SPI_CTRL_READ_94XX (1U << 2)
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#define SPI_ADDR_VLD_94XX (1U << 1)
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#define SPI_CTRL_SpiStart_94XX (1U << 0)
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#define mv_ffc(x) ffz(x)
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@@ -33,12 +33,12 @@
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mr32(reg); \
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} while (0)
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#define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
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#define ior32(reg) inl((unsigned long)(regs + reg))
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#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
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#define ior16(reg) inw((unsigned long)(regs + reg))
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#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
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#define ior8(reg) inb((unsigned long)(regs + reg))
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#define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
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#define ior32(reg) inl((unsigned long)(regs + reg))
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#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
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#define ior16(reg) inw((unsigned long)(regs + reg))
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#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
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#define ior8(reg) inb((unsigned long)(regs + reg))
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static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
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{
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+7
-7
@@ -163,7 +163,7 @@ enum hw_register_bits {
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TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP target free list */
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TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
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TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
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TXQ_MODE_TARGET = 0,
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TXQ_MODE_TARGET = 0,
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TXQ_MODE_INITIATOR = 1,
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TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
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TXQ_PRI_NORMAL = 0,
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@@ -442,7 +442,7 @@ enum error_info_rec {
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CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
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RSP_OVER = (1U << 29), /* rsp buffer overflow */
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RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
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UNK_FIS = (1U << 27), /* unknown FIS */
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UNK_FIS = (1U << 27), /* unknown FIS */
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DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
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SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
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TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
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@@ -455,9 +455,9 @@ enum error_info_rec {
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NAK = (1U << 14), /* NAK rx'd */
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ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
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CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
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OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
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OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
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PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
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NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
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NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
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STP_RES_BSY = (1U << 8), /* STP resources busy */
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BREAK = (1U << 7), /* break received */
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BAD_DEST = (1U << 6), /* bad destination */
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@@ -465,8 +465,8 @@ enum error_info_rec {
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BAD_RATE = (1U << 4), /* cxn rate not supported */
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WRONG_DEST = (1U << 3), /* wrong destination error */
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CREDIT_TO = (1U << 2), /* credit timeout */
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WDOG_TO = (1U << 1), /* watchdog timeout */
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BUF_PAR = (1U << 0), /* buffer parity error */
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WDOG_TO = (1U << 1), /* watchdog timeout */
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BUF_PAR = (1U << 0), /* buffer parity error */
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};
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enum error_info_rec_2 {
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@@ -506,7 +506,7 @@ enum datapres_field {
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};
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/* define task management IU */
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struct mvs_tmf_task{
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struct mvs_tmf_task {
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u8 tmf;
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u16 tag_of_task_to_be_managed;
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};
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+7
-7
@@ -87,8 +87,8 @@ static struct scsi_host_template mvs_sht = {
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};
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static struct sas_domain_function_template mvs_transport_ops = {
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.lldd_dev_found = mvs_dev_found,
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.lldd_dev_gone = mvs_dev_gone,
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.lldd_dev_found = mvs_dev_found,
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.lldd_dev_gone = mvs_dev_gone,
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.lldd_execute_task = mvs_queue_command,
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.lldd_control_phy = mvs_phy_control,
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@@ -98,7 +98,7 @@ static struct sas_domain_function_template mvs_transport_ops = {
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.lldd_clear_aca = mvs_clear_aca,
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.lldd_clear_task_set = mvs_clear_task_set,
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.lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
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.lldd_lu_reset = mvs_lu_reset,
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.lldd_lu_reset = mvs_lu_reset,
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.lldd_query_task = mvs_query_task,
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.lldd_port_formed = mvs_port_formed,
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@@ -728,8 +728,8 @@ static struct pci_device_id __devinitdata mvs_pci_table[] = {
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{ PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
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{ PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
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{
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.vendor = PCI_VENDOR_ID_MARVELL,
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.device = 0x6440,
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.vendor = PCI_VENDOR_ID_MARVELL,
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.device = 0x6440,
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.subvendor = PCI_ANY_ID,
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.subdevice = 0x6480,
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.class = 0,
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@@ -741,8 +741,8 @@ static struct pci_device_id __devinitdata mvs_pci_table[] = {
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{ PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
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{ PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
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{
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.vendor = 0x1b4b,
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.device = 0x9480,
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.vendor = 0x1b4b,
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.device = 0x9480,
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.subvendor = PCI_ANY_ID,
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.subdevice = 0x9480,
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.class = 0,
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+3
-3
@@ -876,7 +876,7 @@ static int mvs_task_prep_ssp(struct mvs_info *mvi,
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#else
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memcpy(buf_cmd + 12, &task->ssp_task.cmd->request->cmd, 16);
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#endif
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} else{
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} else {
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buf_cmd[10] = tmf->tmf;
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switch (tmf->tmf) {
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case TMF_ABORT_TASK:
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@@ -1684,7 +1684,7 @@ int mvs_query_task(struct sas_task *task)
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int rc = TMF_RESP_FUNC_FAILED;
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if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
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struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
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struct scsi_cmnd *cmnd = (struct scsi_cmnd *)task->uldd_task;
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struct domain_device *dev = task->dev;
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struct mvs_device *mvi_dev = dev->lldd_dev;
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struct mvs_info *mvi = mvi_dev->mvi_info;
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@@ -1730,7 +1730,7 @@ int mvs_abort_task(struct sas_task *task)
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}
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if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
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struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
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struct scsi_cmnd *cmnd = (struct scsi_cmnd *)task->uldd_task;
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int_to_scsilun(cmnd->device->lun, &lun);
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rc = mvs_find_tag(mvi, task, &tag);
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+13
-13
@@ -83,7 +83,7 @@ extern const struct mvs_dispatch mvs_94xx_dispatch;
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#define for_each_phy(__lseq_mask, __mc, __lseq) \
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for ((__mc) = (__lseq_mask), (__lseq) = 0; \
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(__mc) != 0 ; \
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(__mc) != 0; \
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(++__lseq), (__mc) >>= 1)
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
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@@ -197,13 +197,13 @@ struct mvs_dispatch {
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};
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struct mvs_chip_info {
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u32 n_host;
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u32 n_phy;
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u32 fis_offs;
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u32 fis_count;
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u32 srs_sz;
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u32 sg_width;
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u32 slot_width;
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u32 n_host;
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u32 n_phy;
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u32 fis_offs;
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u32 fis_count;
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u32 srs_sz;
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u32 sg_width;
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u32 slot_width;
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const struct mvs_dispatch *dispatch;
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};
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@@ -223,7 +223,7 @@ struct mvs_cmd_hdr {
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__le32 lens; /* cmd, max resp frame len */
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__le32 tags; /* targ port xfer tag; tag */
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__le32 data_len; /* data xfer len */
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__le64 cmd_tbl; /* command table address */
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__le64 cmd_tbl; /* command table address */
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__le64 open_frame; /* open addr frame address */
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__le64 status_buf; /* status buffer address */
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__le64 prd_tbl; /* PRD tbl address */
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@@ -238,7 +238,7 @@ struct mvs_port {
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};
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struct mvs_phy {
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struct mvs_info *mvi;
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struct mvs_info *mvi;
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struct mvs_port *port;
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struct asd_sas_phy sas_phy;
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struct sas_identify identify;
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@@ -403,12 +403,12 @@ struct mvs_info {
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#ifndef DISABLE_HOTPLUG_DMA_FIX
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void *bulk_buffer;
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dma_addr_t bulk_buffer_dma;
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#define TRASH_BUCKET_SIZE 0x20000
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#define TRASH_BUCKET_SIZE 0x20000
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#endif
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struct mvs_slot_info slot_info[0];
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};
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struct mvs_prv_info{
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struct mvs_prv_info {
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u8 n_host;
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u8 n_phy;
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u16 reserve;
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@@ -455,7 +455,7 @@ int mvs_queue_command(struct sas_task *task, const int num,
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int mvs_abort_task(struct sas_task *task);
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int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
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int mvs_clear_aca(struct domain_device *dev, u8 *lun);
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int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
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int mvs_clear_task_set(struct domain_device *dev, u8 *lun);
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void mvs_port_formed(struct asd_sas_phy *sas_phy);
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void mvs_port_deformed(struct asd_sas_phy *sas_phy);
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int mvs_dev_found(struct domain_device *dev);
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+20
-24
@@ -30,28 +30,23 @@
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static u8 SPICmd[16];
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#ifndef IDENTIFY_SPI
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u8 DEFAULT_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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u8 DEFAULT_SPI_CMD[16] = {
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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};
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#else
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static u8 ATMEL_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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static u8 ATMEL_SPI_CMD[16] = {
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x52, 0x62, 0x15
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};
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static u8 WINBOND_SPI_CMD[16] =
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{
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0xC7, 0xAB
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static u8 WINBOND_SPI_CMD[16] = {
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0xC7, 0xAB
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};
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static u8 ATMEL_SPI_CMD_41a_021[16] =
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{
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/* 0 1 2 3 4 5 6 7 8 9 10 11*/
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0xD8, 0x60, 0x9F, 0x36, 0x39, 0x3C
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static u8 ATMEL_SPI_CMD_41a_021[16] = {
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/* 0 1 2 3 4 5 6 7 8 9 10 11*/
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0xD8, 0x60, 0x9F, 0x36, 0x39, 0x3C
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};
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static u8 EON_F20_SPI_CMD[16] =
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{
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static u8 EON_F20_SPI_CMD[16] = {
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0x06, 0x04, 0x05, 0x01, 0x03, 0x02, 0x20, 0x60, 0x90
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};
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#endif
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@@ -261,9 +256,9 @@ static int spi_readbuf(struct mvs_info *mvi, u32 addr, u8 *data, u32 count)
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static u8 mvverifychecksum(u8 *address, u32 Size)
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{
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u8 checkSum = 0;
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u32 temp = 0;
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u32 temp = 0;
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for (temp = 0; temp < Size ; temp++)
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for (temp = 0; temp < Size; temp++)
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checkSum += address[temp];
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return checkSum;
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@@ -272,7 +267,8 @@ static u8 mvverifychecksum(u8 *address, u32 Size)
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static bool mvui_init_param(struct mvs_info *mvi,
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struct hba_info_main *hba_info_para)
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{
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u32 param_flash_addr = PARA_OFF;
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u32 param_flash_addr = PARA_OFF;
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if (!mvi)
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return false;
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@@ -282,14 +278,14 @@ static bool mvui_init_param(struct mvs_info *mvi,
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}
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mv_dprintk("Init flash rom ok,flash type is 0x%x.\n", mvi->flashid);
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/* step 1 read param from flash offset = 0x3FFF00 */
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spi_readbuf(mvi, param_flash_addr, \
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(u8 *)hba_info_para, FLASH_PARA_SIZE);
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spi_readbuf(mvi, param_flash_addr, (u8 *)hba_info_para,
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FLASH_PARA_SIZE);
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/* step 2 check the signature first */
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if (hba_info_para->signature[0] == 'M' && \
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hba_info_para->signature[1] == 'R' && \
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hba_info_para->signature[2] == 'V' && \
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hba_info_para->signature[3] == 'L' && \
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if (hba_info_para->signature[0] == 'M' &&
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hba_info_para->signature[1] == 'R' &&
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hba_info_para->signature[2] == 'V' &&
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hba_info_para->signature[3] == 'L' &&
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(!mvverifychecksum((u8 *)hba_info_para, FLASH_PARA_SIZE))) {
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return true;
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}
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+6
-6
@@ -46,20 +46,20 @@
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#define SPI_INS_WREN 0
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#define SPI_INS_WRDI 1
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#define SPI_INS_RDSR 2
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#define SPI_INS_WRSR 3
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#define SPI_INS_RDSR 2
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#define SPI_INS_WRSR 3
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#define SPI_INS_READ 4
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#define SPI_INS_RPOG 5
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#define SPI_INS_SERASE 6
|
||||
#define SPI_INS_CERASE 7
|
||||
#define SPI_INS_RDID 8
|
||||
#define SPI_INS_RDID 8
|
||||
#define SPI_INS_PRSEC 9
|
||||
#define SPI_INS_UPTSEC 10
|
||||
#define SPI_INS_RDPT 11
|
||||
#define SPI_INS_RDPT 11
|
||||
|
||||
|
||||
#define MAX_PD_IN_PD_PAGE_FLASH 128
|
||||
#define FLASH_PARA_SIZE (sizeof(struct hba_info_main))
|
||||
#define FLASH_PARA_SIZE (sizeof(struct hba_info_main))
|
||||
#define rounding_mask(x, mask) (((x)+(mask))&~(mask))
|
||||
#define rounding(value, align) rounding_mask(value, \
|
||||
(typeof(value)) (align-1))
|
||||
@@ -67,7 +67,7 @@
|
||||
|
||||
#define PAGE_INTERVAL_DISTANCE 0x100
|
||||
|
||||
struct hba_info_main{
|
||||
struct hba_info_main {
|
||||
u8 signature[4];
|
||||
u8 reserve[52];
|
||||
u64 sas_address[8];
|
||||
|
||||
+2
-2
@@ -1982,7 +1982,7 @@ static u8 mvst_response_ssp_command(struct mvs_info *mvi, uint32_t rx_desc)
|
||||
|
||||
}
|
||||
/*
|
||||
else if(slot->slot_tgt_port->port_attr == MVST_INIT_PORT){
|
||||
else if (slot->slot_tgt_port->port_attr == MVST_INIT_PORT) {
|
||||
mv_dprintk("Found recevied command[%p] but not set
|
||||
as tgt port[0x%x].\n", slot->slot_scst_cmd,
|
||||
slot->slot_tgt_port->port_attr);
|
||||
@@ -2118,7 +2118,7 @@ static void mvst_enable_tgt_port(struct mvs_info *mvi, u8 phyid)
|
||||
struct asd_sas_phy *sas_phy;
|
||||
u8 id = 0;
|
||||
|
||||
#if 0
|
||||
#if 0
|
||||
u8 j = 0, i = 0
|
||||
/*enable all the phy within the same port*/
|
||||
for (id = 0, j = 0; id < mvi->chip->n_phy; id++) {
|
||||
|
||||
+34
-39
@@ -62,25 +62,21 @@ extern unsigned long mvst_trace_flag;
|
||||
*/
|
||||
#undef ENTER_TRACE
|
||||
#if defined(ENTER_TRACE)
|
||||
#define ENTER(x) \
|
||||
do {printk(KERN_NOTICE "mvsas : Entering %s()\n", x); } while (0)
|
||||
#define LEAVE(x) \
|
||||
do {printk(KERN_NOTICE "mvsas : Leaving %s()\n", x); } while (0)
|
||||
#define ENTER_INTR(x) \
|
||||
do {printk(KERN_NOTICE "mvsas : Entering %s()\n", x); } while (0)
|
||||
#define LEAVE_INTR(x) \
|
||||
do {printk(KERN_NOTICE "mvsas : Leaving %s()\n", x); } while (0)
|
||||
#define ENTER(x) printk(KERN_NOTICE "mvsas : Entering %s()\n", x)
|
||||
#define LEAVE(x) printk(KERN_NOTICE "mvsas : Leaving %s()\n", x)
|
||||
#define ENTER_INTR(x) printk(KERN_NOTICE "mvsas : Entering %s()\n", x)
|
||||
#define LEAVE_INTR(x) printk(KERN_NOTICE "mvsas : Leaving %s()\n", x)
|
||||
#else
|
||||
#define ENTER(x) do {} while (0)
|
||||
#define LEAVE(x) do {} while (0)
|
||||
#define ENTER_INTR(x) do {} while (0)
|
||||
#define ENTER_INTR(x) do {} while (0)
|
||||
#define LEAVE_INTR(x) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef MV_DEBUG
|
||||
#define DEBUG(x) do {x; } while (0);
|
||||
#define DEBUG(x) (x)
|
||||
#else
|
||||
#define DEBUG(x) do {} while (0);
|
||||
#define DEBUG(x) do {} while (0)
|
||||
#endif
|
||||
|
||||
#define BUFFER_PACKED __packed
|
||||
@@ -99,8 +95,8 @@ extern unsigned long mvst_trace_flag;
|
||||
#define MVST_TMF 0x1
|
||||
|
||||
/* defines for address frame types */
|
||||
#define ADDRESS_IDENTIFY_FRAME 0x00
|
||||
#define ADDRESS_OPEN_FRAME 0x01
|
||||
#define ADDRESS_IDENTIFY_FRAME 0x00
|
||||
#define ADDRESS_OPEN_FRAME 0x01
|
||||
|
||||
/* defines for target mode action */
|
||||
#define MVSAS_ENABLE_TGT 0x01
|
||||
@@ -122,8 +118,8 @@ extern unsigned long mvst_trace_flag;
|
||||
|
||||
/* TM failed */
|
||||
#define MVST_TM_COMPL 0x00
|
||||
#define MVST_TM_INVALID_FR 0x02
|
||||
#define MVST_TM_NOT_SUPPORT 0x04
|
||||
#define MVST_TM_INVALID_FR 0x02
|
||||
#define MVST_TM_NOT_SUPPORT 0x04
|
||||
#define MVST_TM_FAILED 0x05
|
||||
#define MVST_TM_SUCCEED 0x08
|
||||
#define MVST_TM_INCRT_LUN 0x09
|
||||
@@ -136,7 +132,7 @@ extern unsigned long mvst_trace_flag;
|
||||
#define MVST_EXEC_READ 0x1
|
||||
#define MVST_EXEC_WRITE 0x2
|
||||
|
||||
enum mvst_msg_state{
|
||||
enum mvst_msg_state {
|
||||
MSG_QUEUE_IDLE = 0,
|
||||
MSG_QUEUE_PROC,
|
||||
MSG_QUEUE_NO_START
|
||||
@@ -157,9 +153,9 @@ struct mvst_msg {
|
||||
|
||||
#define MSG_QUEUE_DEPTH (MVS_MAX_PHYS)
|
||||
|
||||
#define MVST_TGT_PORT 1
|
||||
#define MVST_INIT_PORT 2
|
||||
#define MVST_INIT_TGT_PORT 3
|
||||
#define MVST_TGT_PORT 1
|
||||
#define MVST_INIT_PORT 2
|
||||
#define MVST_INIT_TGT_PORT 3
|
||||
|
||||
struct mvst_msg_queue {
|
||||
u8 msg_state;
|
||||
@@ -286,7 +282,7 @@ struct mvs_cmd_header {
|
||||
/* DWORD 10 - 11 */
|
||||
__le64 prd_tbl; /* PRD tbl address */
|
||||
/* DWORD 12-15 */
|
||||
__le32 reserved[4];
|
||||
__le32 reserved[4];
|
||||
} BUFFER_PACKED;
|
||||
|
||||
/* for command table */
|
||||
@@ -390,17 +386,17 @@ struct mv_ssp_response_iu {
|
||||
u8 data[0];
|
||||
} BUFFER_PACKED;
|
||||
|
||||
#define NO_DATA 0
|
||||
#define RESPONSE_DATA 1
|
||||
#define SENSE_DATA 2
|
||||
#define NO_DATA 0
|
||||
#define RESPONSE_DATA 1
|
||||
#define SENSE_DATA 2
|
||||
|
||||
#define TASK_MANAGE_COMP 0x00
|
||||
#define INVALID_FRAME 0x02
|
||||
#define TASK_MANAGE_UNSUPPORT 0x04
|
||||
#define TASK_MANAGE_FAILED 0x05
|
||||
#define TASK_MANAGE_SUCCESS 0x08
|
||||
#define INCORRECT_LOGICAL_UNIT 0x09
|
||||
#define OVERLAPPED_TAG 0x0a
|
||||
#define TASK_MANAGE_COMP 0x00
|
||||
#define INVALID_FRAME 0x02
|
||||
#define TASK_MANAGE_UNSUPPORT 0x04
|
||||
#define TASK_MANAGE_FAILED 0x05
|
||||
#define TASK_MANAGE_SUCCESS 0x08
|
||||
#define INCORRECT_LOGICAL_UNIT 0x09
|
||||
#define OVERLAPPED_TAG 0x0a
|
||||
|
||||
|
||||
/* SSP Command Table */
|
||||
@@ -467,7 +463,7 @@ struct mvs_compl_queue {
|
||||
} BUFFER_PACKED;
|
||||
|
||||
|
||||
enum mvst_tgt_host_action_t{
|
||||
enum mvst_tgt_host_action_t {
|
||||
DISABLE_TARGET_MODE = 0,
|
||||
ENABLE_TARGET_MODE = 1,
|
||||
EXIT_TARGET_MODE = 0xff
|
||||
@@ -495,8 +491,8 @@ struct mvst_sess {
|
||||
|
||||
/* Open Address Frame */
|
||||
struct open_address_frame {
|
||||
union{
|
||||
struct{
|
||||
union {
|
||||
struct {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u8 initiator:1;
|
||||
u8 protocol:3;
|
||||
@@ -513,7 +509,6 @@ struct open_address_frame {
|
||||
u8 feature:4;
|
||||
#endif /* __BIG_ENDIAN_BITFIELD */
|
||||
__be16 connect_tag;
|
||||
;
|
||||
};
|
||||
struct {
|
||||
__be16 received_tag;
|
||||
@@ -553,7 +548,7 @@ struct mvst_cmd {
|
||||
dma_addr_t dma_handle;
|
||||
struct mvst_port *cmd_tgt_port;
|
||||
u32 transfer_len;
|
||||
u32 finished_len;
|
||||
u32 finished_len;
|
||||
void *transfer_buf;
|
||||
void *org_transfer_buf;
|
||||
};
|
||||
@@ -606,7 +601,7 @@ struct mvst_port {
|
||||
int port_id;
|
||||
u8 port_attached;
|
||||
u8 wide_port_phymap; /* save phy id */
|
||||
u8 port_attr;
|
||||
u8 port_attr;
|
||||
u64 sas_addr;
|
||||
u64 att_sas_addr;
|
||||
struct list_head slot_list;
|
||||
@@ -623,10 +618,10 @@ int mvst_init(void);
|
||||
void mvst_int_port(struct mvs_info *mvi, u32 id);
|
||||
u32 mvst_check_port(struct mvs_info *mvi, u8 phy_id);
|
||||
void mvst_init_tgt_port(struct mvs_info *mvi);
|
||||
#define MVST_IN_TARGET_MODE(mvi) (mvi->flags & MVF_TARGET_MODE_ENABLE)
|
||||
#define PHY_IN_TARGET_MODE(dev) (dev & PORT_DEV_SSP_TRGT) ? 1 : 0
|
||||
#define MVST_IN_TARGET_MODE(mvi) ((mvi)->flags & MVF_TARGET_MODE_ENABLE)
|
||||
#define PHY_IN_TARGET_MODE(dev) (((dev) & PORT_DEV_SSP_TRGT) ? 1 : 0)
|
||||
|
||||
#endif /* #ifdef _MVSAST_H */
|
||||
#endif /*SUPPORT_TARGET*/
|
||||
#endif /*SUPPORT_TARGET*/
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user